• The Journal of Information Technology
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• v.7 no.3
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• pp.119-126
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• 2004

In multicast traffic, an input can request to connect to up to a certain number of outputs. This reviews the multicast nonblocking multistage interconnection networks. In a multistage interconnection network each stage consists of crossbars of the same size. This paper focuses on the three-stage network and its recursive extensions. Not only will this article bring the literature upto date, but it also will provide some fresh viewpoints to either clarify or simplify some issues.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.4
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• pp.357-364
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• 1987

In this paper we consider the performance Analysis of multistage interconnection network, which is major parts of multi-processor system. We review the Hardware configuration of STAR network system using base-line interconnection network and obtain the probability of clustering basing on analytical model. In addition, Instead of Baseline interconnection system, mentioned above, STAR network system using delta network is considered and TWO probability mentioned above is obtained, finally the comparative result is shown in the figure.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.569-571
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• 1995

This paper compares the simulated annealing and the Hopfield neural network method for an optimal routing in a multistage interconnection network(MIN). The MIN provides a multiple number of paths for ATM cells to avoid cell conflict. Exhaustive search always finds the optimal path, but with heavy computation. Although greedy method sets up a path quickly, the path found need not be optimal. The simulated annealing can find an sub optimal path in time comparable with the greedy method.

• Journal of KIISE:Information Networking
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• v.29 no.6
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• pp.738-748
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• 2002

In this paper, a performance evaluation model of the Multistage Interconnection Network(MIN) with the multiple-buffered crossbar switches is Proposed and examined. Buffered switch technique is well known to solve the data collision problem of the MIN. The proposed evaluation model is developed by investigating the transfer patterns of data packets in a switch with output-buffers. The performance of the multiple-buffered${\alpha}{\times}{\alpha}$ crossbar switch is analyzed. Steady state probability concept is used to simplify the analyzing processes, Two important parameters of the network performance, throughput and delay, are then evaluated, To validate the proposed analysis model, the simulation is carried out on a Baseline network that uses the multiple buffered crossbar switches. Less than 2% differences between analysis and simulation results are observed. It is also shown that the network performance is significantly improved when the small number of buffer spaces is given. However, the throughput elevation is getting reduced and network delay becomes increasing as more buffer spaces are added in a switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.6
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• pp.675-685
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• 1989

The interconnection network is an integral part of parallel processing system. The multistage interconnection networks(MINs) have been the objects of intense research in recent years. In this paper, simulation techniques for circuit switchign MIN are extended to allow the performance evaluation of partitioned ADM/IADM network. Based on simulation data, the relationship between the netwrok performance, the partitioning scheme employed, and the conflict resolution strategies used within the network is enumerated. It is shown that IADM network coupled with the use of the hold strategy produces the best network operation in terms of RST (Request Service Time).

• The Transactions of the Korea Information Processing Society
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• v.4 no.9
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• pp.2259-2268
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• 1997

Multistage interconnection networks(MINs) provide a high-bandwidth communication between processors and/or memory modules in a cost-effective way. In this paper, we propose a class of multipath MINs, called the Augmented Modified Delta(AMD) network, and analyze its performance and reliability. The salient features of the AMD network include fault-tolerant capability, modular structure, and high performance, which are essential for real-time parallel/distributed processing environments. The class of the AMD network retains well-known characteristics of the Kappa network, but it's design procedure is more systematic. Like Delta networks, all the AMD networks are topologically equivalent with each other.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6B
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• pp.563-574
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• 2004

In this paper, we propose a new class of MIN(Multistage Interconnection Network) called Combine MIN which combines static network topology and apimic network topology. Combine U provides multiple paths at a hardware cost lower than that of MIN with unique path property. Combine MIN can be constructed suitable for localized communication by providing the shortcut path and multiple paths inside the processor-memory cluster which has frequent data communications. According to the results of analysis and simulation for performance evaluation, Combine MIN shows higher performance than MINs of the same network size in the highly localized communication Therefore, Combine MIN can be used as an attractive interconnection network for parallel applications with a localized communication pattern in shared-memory multiprocessor systems.

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.35-43
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• 2004

In packet switching using multistage interconnection networks (MIN's), it is generally assumed that the packet movements successively propagate from the last stage to the first stage in one network cycle. However, Ding and Bhuyan has shown that the network performance can be significantly improved if the packet movements are confined within each pair of adjacent stages using small clock cycles. In this paper, an analytical model for evaluating the performance of input-buffered MlN's employing this network cycle approach is proposed, The effectiveness of the proposed model is confirmed by comparing results from the simulation as well as from Ding and Bhuyan model.

• Journal of Institute of Control, Robotics and Systems
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• v.8 no.3
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• pp.256-263
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• 2002

Optical Multistage Interconnection Networks(OMINs) comprising photonic switches have been studied extensively as important interconnecting building blocks for communication networks and parallel computing systems. A basic element of photonic switching networks is a 2$\times$2 directional coupler with two inputs and two outputs. This paper is concerned with the diagnosis of cross-talk-faults in OMINs. As the size of today's network becomes very large, the conventional diagnosis methods based on tests and simulation have become inefficient, or even more, impractical. In this paper, we propose a simple and easily implementable algorithm for detection and isolation of the single crosstalk-fault in OMINs. Specifically, we develope an algorithm fur the isolation of the source fault in switching elements whenever the single crosstalk-fault is detected in OMINS. The proposed algorithm is illustrated by an example of 16$\times$16 banyan network.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.1
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• pp.24-32
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• 2002

This paper is concerned with the fault diagnosis for stuck-at faults of a multistage interconnection network(MIM) which is a kind of interconnection networks in multicomputer systems. Up to the present, a fault diagnosis scheme has dealt with a fault model of all types, which results in complicated algorithms. In the literature, it is shown that a number of steps and computation are required for the fault detection and isolation algorithms for a class of MINs. In this paper, we propose a simple and easily implementable algorithm for the detection and isolation of the stuck-at fault in MIM. specifically, we develope an at algorithm for the isolation of the source fault in switching elements whenever tile stuck-at fault is detected in MINs. After all, the proposed algorithm is illustrated by an example of 16$\times$16 baseline networks of MINs.