• 제어로봇시스템학회:학술대회논문집
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• 2001.10a
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• pp.140.3-140
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• 2001

This paper analyzes a blocking that is due to shared resource in multiprocessor system. A proposed analysis for shared resource suggests a scalable and amendable scheduling method about task allocation. An equation of shared resource blocking is proposed by a throughput at common bus and a ratio of throughput during time period, it is included a parameter of tasks scheduling. Using this equation, a new guideline for task allocation of multiprocessor is presented. Finally, in proposed system a model simulations for the proposed blocking model is given by a deterministic ratio of shared resource.

• Proceedings of the IEEK Conference
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• summer
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• pp.39-41
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• 2004

In this paper, I propose a thread scheduling policy for faster packet processing on the network processors with multithreaded multiprocessor architecture. To implement the proposed policy, I derived several basic parameters related to the thread scheduling and included a new parameter representing the packet contents and the features of the multithreaded architecture. Through the empirical study using a network processor, I proved the proposed scheduling ploicy provides better throughput and load balancing compared to the generally used thread scheduling policy.

• Journal of Korea Multimedia Society
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• v.8 no.12
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• pp.1605-1612
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• 2005

This paper presents the knowledge and experience we obtained by employing multiprocessor systems as a computer simulation design verification to study high-performance computing system. This paper also describes a case study of symmetric multiprocessors (SMP) kernel on a 32 CPUs CC-NUMA architecture using an actual architecture. A small group of CPUs of CC-NUMA, high-performance computer system, is clustered into a processing node or cluster. By simulating the system design verification tools; we discussed SMP OS kernel on a CC-NUMA multiprocessor architecture performance which is $32\%$ of the total execution time and remote memory access latency is occupied $43\%$ of the OS time. In this paper, we demonstrated our simulation results for multiprocessor, high-performance computing system performance, using simulation-based design verification.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.57-65
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• 2010

In this paper, we propose the structure of heterogeneous multiprocessor's concept, which is the structure of the new type of the robot controller, and we introduce an integrating structure method, which is distributed multiprocessor within controller using sRIO. We also perform the computer simulation with using the sRIO IP core which was designed within FPGA as the method for implementation of integrated heterogeneous multiprocessor by sRIO communication. Thus, we verify the result.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.408-411
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• 1999

Microarchitecture simulator is an important tool to verify and optimize the microarchitecture of a new microprocessor. Moreover. it can be use as a performance simulator to estimate the target microprocessor′s performance. And system software designers can use it as a software developing environment. This paper describes a "microarchitecture simulator for on-chip Multiprocessor microprocessor". It is a program-driven and cycle-based simulator that can execute simultaneous mutithreading benchmarks. We verified the microarchitecture of a new on-chip multiprocessor microprocessor with it and did performance simulations to estimate the performance of the on-chip multiprocessor microprocessor.

• Electronics and Telecommunications Trends
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• v.13 no.5 s.53
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• pp.11-22
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• 1998

Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.723-724
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• 2006

Exploiting the instruction level parallelism encountered with the limit. Single chip multiprocessor was introduced to overcome the limit of traditional processor using the instruction level parallelism. Also, a branch miss prediction is one of the causes that reduce the processor performance. In order to overcome the problems, in this paper, we make single chip multiprocessor having the idle core execute the two control flow of conditional branch. This scheme is a kind of multi-path execution technique based on single chip multiprocessor architecture.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.12 no.5
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• pp.505-518
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• 1987

In this paper, the 2-level and 3-level types of PWM technique have been analyzed, and a multiprocessor has been designed as controller for these two types of PWM inverters. Designed multiprocessor employing a hierarchical structure of a SUPERVISORY PROCESSOR which interconnects three LOCAL PROCESSOR through a common memory technique has showed as elaborate digital control characteristic. Using this multiprocessor configuration the system could gain a great degree of freedom in change of software. Also software was simpler than a single processor configuration.

• 제어로봇시스템학회:학술대회논문집
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• 1987.10b
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• pp.426-430
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• 1987

The reliability is the critical issue in many computer applications, particularly in process control system. In this paper we describe how to achieve the reliability improvement in controller system based multiprocessor. The proposed method is accomplished by using the techniques of fault detection, fault isolation, safe action, and fault diagnosis.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.