• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.3
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• pp.60-68
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• 1994

In this paper, the multiplicative algorithm of two polynomials over finite field GF(($p^{m}$) is presented. Using the presented algorithm, the multiple-valued multiplier of the serial input-output modular structure by CCD is constructed. This multiple-valued multiplier on CCD is consisted of three operation units: the multiplicative operation unit, the modular operation unit, and the primitive irreducible polynomial operation unit. The multiplicative operation unit and the primitive irreducible operation unit are composed of the overflow gate, the inhibit gate and mod(p) adder on CCD. The modular operation unit is constructed by two mod(p) adders which are composed of the addition gate, overflow gate and the inhibit gate on CCD. The multiple-valued multiplier on CCD presented here, is simple and regular for wire routing and possesses the property of modularity. Also. it is expansible for the multiplication of two elements on finite field increasing the degree mand suitable for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.4
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• pp.55-61
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• 1994

The multiple valued logic(MVL) circuit with ROM type using current mode CMOS is presented in this paper. This circuit is composed of the multiple valued-to-binary(MV/B) decoder and the selection circuit. The MV/B decoder decodes the single input multiple valued signal to N binary signal, and the selection circuits is composed N$\times$N array of the selecion cells with ROM types. The selection cell is realized with the current mirror circuits and the inhibit circuits. The presented circuit is suitable for designing the circuit of MVL functions with independent variables, and reduces the number of selection cells for designing the circuit of symmetric MVL functions as many as {($N^2$-N)/2}+N. This circuit possess features of simplicity. expansibility for array and regularity, modularity for the wire routing. Also, it is suitable for VLSI implementation.

• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.5
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• pp.1-7
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• 1983

Generally, multiple-valued logic algebra is based on the number system of modulo-M. In this paper, characters a, b, c‥… each of them represents the independent state, are regarded as the elements of the symbolic multiple-valued logic. By using the set theory, the symbolic multiple - valued logic and their functions are defined. And Varation for the symbolic logic function due to the variation of a variable and their properties are suggested and analized. With these variations, the MacLaurin's and Taylor's Series expansions of the symbolic logic functions are proposed and proved.

• Journal of the Korean Institute of Intelligent Systems
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• v.19 no.1
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• pp.13-18
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• 2009

Usually, human emotions are vague and change diversely on the basis of the stimulus from the outside. Plutchik classified the fundamental behavioral patterns into eight patterns, named each of them a genuine emotion, and furthermore suggested mixed emotions using a combination of genuine emotions. In this paper, we propose a method for processing Plutchik's emotion model using Multiple Valued Logic(MVL) Automata Model which utilizes the properties of difference in Multiple Valued Logic functions. This proposed emotion processing model can be widely applied to the analysis and processing of emotion data.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1274-1276
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• 1993

We have designed a multiple-valued fuzzy Approximate Analogical-Reseaning system (AARS). The system uses a similarity measure of fuzzy sets and a threshold of similarity ST to determine whether a rule should be fired, with a Modification Function inferred from the Similarity Measure to deduce a consequent. Multiple-valued basic fuzzy blocks are used to construct the system. A description of the system is presented to illustrate the operation of the schema. The results of simulations show that the system can perform about 3.5 x 106 inferences per second. Finally, we compare the system with Yamakawa's chip which is based on the Compositional Rule of Inference (CRI) with Mamdani's implication.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.22-32
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• 2004

In this paper, we proposed MOVAG(Multi Output Value Array Graphs) based on OVAG by Honghai Jiang to construct multiple valued logic function The MDD(Muliple-valued Decision Diagra) needs many processing time and efforts in circuit design for given multi-variable function by D.M.Miller, and we designed a MOVAG which has reduce the data processing time and low complexity. We propose the construction algorithm and input matrix selection algorithm and we designed the multiple-valued logic circuit using T-gate and verified by simulation results.

• Journal of the Institute of Convergence Signal Processing
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• v.6 no.3
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• pp.134-142
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• 2005

The implementation of Multiple-Valued Logic(MVL) based on Current-Mode CMOS Logic(CMCL) circuits has recently been achieved. In this paper, four-valued Unary Multiple-Valued logic functions are synthesized using current-mode CMOS logic circuits. We properly make use of the fact that the CMCL addition of logic values represented using discrete current values can be performed at no cost and that negative logic values are readily available via reversing the direction of current flow. A synthesis process for CMCL circuits is based upon a logically complete set of basic elements. Proposed algorithm results in less expensive realization than those achieved using existing techniques in terms of the number of transistors needed. As an alternative to the cost-table techniques Universal Unary Programmable Circuit (UUPC) for a unary function is also proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.5
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• pp.503-510
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• 1989

This paper represents a method which construct Combinational Mutiple Valued Logic circuits. First, it constructs Combinational Multiple Valued Logic Cell as the input variable, Then, it can be applied to the general case by expanding ti, thus these series of process is simple and regular. The construction theory of Combinational Multiple Valued Logic circuits, representes here has regularity, simplicity and modularity, especially, in case imput variables are incresed this theory also has characteristics of expansion.

• Journal of IKEEE
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• v.1 no.1 s.1
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• pp.111-119
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• 1997

This paper presented a method of extracting algorithm for Edge Multiple-Valued Decision Diagrams(EMVDD), a new data structure, from Binary Decision Diagram(BDD) which is resently used in constructing the digital logic systems based on the graph theory. And we discussed the function minimization method of the n-variables multiple-valued functions. The proposed method has the visible, schematical and regular properties.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.2 no.3
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• pp.215-220
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• 2002

This paper proposes a method to apply the Backpropagation(BP) algorithm of MVL(Multi-Valued Logic) Neural Network to pattern recognition. It extracts the property of an object density about an original pattern necessary for pattern processing and makes the property of the object density mapped to MVL. In addition, because it team the pattern by using multiple valued logic, it can reduce time f3r pattern and space fer memory to a minimum. There is, however, a demerit that existed MVL cannot adapt the change of circumstance. Through changing input into MVL function, not direct input of an existed Multiple pattern, and making it each variable loam by neural network after calculating each variable into liter function. Error has been reduced and convergence speed has become fast.