• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.221.2-221.2
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• 2015

Graphene is very interesting 2 dimensional material providing unique properties. Especially, graphene has been investigated as a stretchable and transparent conductor due to its high mobility, high optical transmittance, and outstanding mechanical properties. On the contrary, high sheet resistance of extremely thin monolayer graphene limits its application. Artificially stacked multilayer graphene is used to decrease its sheet resistance and has shown improved results. However, stacked multilayer graphene requires repetitive and unnecessary transfer processes. Recently, growth of multilayer graphene has been investigated using a chemical vapor deposition (CVD) method but the layer controlled synthesis of multilayer graphene has shown challenges. In this paper, we demonstrate controlled growth of multilayer graphene using a two-step process with multi heating zone low pressure CVD. The produced graphene samples are characterized by optical microscope (OM) and scanning electron microscopy (SEM). Raman spectroscopy is used to distinguish a number of layers in the multilayer graphene. Its optical and electrical properties are also analyzed by UV-Vis spectrophotometer and probe station, respectively. Atomic resolution images of graphene layers are observed by high resolution transmission electron microscopy (HRTEM).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

• Proceedings of the Korean Vacuum Society Conference
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• 2009.08a
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• pp.207-207
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• 2009

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.3-17
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• 2003

.Package Trend -> Memory : Lighter, Thinner, Smaller & High Density => SiP, 3D Stack -> MPU : High Pin Counts & Multi-functional => FCBGA .Interposer Trend -> Via - Unfilled Via => Filled Via - Staggered Via => Stacked Via -> Emergence of All-layer Build-up Processes -> Interposer Material Requirement => Low CTE, Low $D_{k}$, Low $D_{f}$, Halogen-free .New Technology Concept -> Embedded Passives, Imprint, MLTS, BBUL etc.

• Journal of the Semiconductor & Display Technology
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• v.8 no.1
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• pp.13-17
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• 2009

In PRAM applications, the devices can be made for both binary and multi-state storage. The ability to attain intermediate stages comes either from the fact that some chalcogenide materials can exist in configurations that range from completely amorphous to completely crystalline or from designing device structure such a way that mimics multiple phase chase phenomena in single cell. We have designed stack-structured phase change memory cell which operates as multi-state storage. Amorphous $Ge_xTe_{100-x}$ chalcogenide materials were stacked and a diffusion barrier was chosen for each stack layers. The device is operated by crystallizing each chalcogenide material as sequential manner from the bottom layer to the top layer. The amplitude of current pulse and the duration of pulse width was fixed and number of pulses were controlled to change overall resistance of the phase change memory cell. To optimize operational performance the thickness of each chalcogenide was controlled based on simulation results.

• Korean Journal of Materials Research
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• v.22 no.8
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• pp.403-408
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• 2012

A sample of ultra low carbon IF steel was processed by six-layer stack accumulative roll-bonding (ARB) and annealed. The ARB was conducted at ambient temperature after deforming the as-received material to a thickness of 0.5 mm by 50% cold rolling. The ARB was performed for a six-layer stacked, i.e. a 3 mm thick sheet, up to 3 cycles (an equivalent strain of ~7.0). In each ARB cycle, the stacked sheets were, first, deformed to 1.5 mm thickness by 50% rolling and then reduced to 0.5 mm thickness, as the starting thickness, by multi-pass rolling without lubrication. The specimen after 3 cycles was then annealed for 0.5 h at various temperatures ranging from 673 to 973 K. The microstructural evolution with the annealing temperature for the 3-cycle ARB processed IF steel was investigated in detail by transmission electron microscopy observation. The ARB processed IF steel exhibited mainly a dislocation cell lamella structure with relatively high dislocation density in which the subgrains were partially observed. The selected area diffraction (SAD) patterns suggested that the misorientation between neighboring cells or subgrains was very small. The thickness of the grains increased in a gradual way up to 873 K, but above 898 K it increased drastically. As a result, the grains came to have an equiaxed morphology at 898 K, in which the width and the thickness of the grains were almost identical. The grain growth occurred actively at temperatures above 923 K.

• Journal of the Korean Vacuum Society
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• v.19 no.3
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• pp.217-223
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• 2010

We grew multi-stacked InAs/$In_{0.1}Ga_{0.9}As$ DWELL (dot-in-a-well) structure by metal organic chemical vapor deposition and investigated optical properties by photoluminescence and I-V characteristics by dark current measurement. When stacking InAs quantum dots (QDs) with same growth parameter, the size and density of QDs were changed, resulting in the bimodal emission peak. By decreasing the flow rate of TMIn, we achieved the uniform multi-stacked QD structure which had the single emission peak and high PL intensity. As the growth temperature of n-type GaAs top contact layer (TCL) is above $600^{\circ}C$, the PL intensity severely decreased and dark current level increased. At bias of 0.5 V, the activation energy for temperature dependence of dark current decreased from 106 meV to 48 meV with increasing the growth temperature of n-type GaAs TCL from 580 to $650^{\circ}C$. This suggest that the thermal escape of bounded electrons and non-radiative transition become dominant due to the thermal inter-diffusion at the interface between InAs QDs and $In_{0.1}Ga_{0.9}As$ well layer.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.3
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• pp.273-279
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• 2006

High-$T_c$ superconducting (HTSC) power cable is one of the interesting parts in power application using HTSC wire. However, its stacked structure makes the current distribution between conducting layers non-uniform due to difference between self inductances of conducting layers and mutual inductances between two conducting layers, which results in lower current transmission capacity of HTSC power cable. In this paper, the transport current distribution between conducting layers was investigated through the numerical analysis for the equivalent circuit of HTSC power cable with a shield layer, and compared with the case of without a shield layer. The transport current distribution due to the increase of the contact resistance in each layer was improved. However, its magnetization loss increased as the contact resistance increased. It was confirmed from the analysis that the shield layer was contributed to the improvement of the current distribution between conducting layers if the winding direction and the pitch length were properly chosen.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.257-257
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• 2010

One of the critical issues for applications of flexible organic thin film transistors (OTFTs) for flexible electronic systems is the electrical stabilities of the OTFT devices, including variation of the current on/off ratio ($I_{on}/I_{off}$), leakage current, threshold voltage, and hysteresis, under repetitive mechanical deformation. In particular, repetitive mechanical deformation accelerates the degradation of device performance at the ambient environment. In this work, electrical stabilities of the pentacene organic thin film transistors (OTFTs) employing multi-stack hybrid encapsulation layers were investigated under mechanical cyclic bending. Flexible bottom-gated pentacene-based OTFTs fabricated on flexible polyimide substrate with poly-4-vinyl phenol (PVP) dielectric as a gate dielectric were encapsulated by the plasma-deposited organic layer and atomic layer deposited inorganic layer. For cyclic bending experiment of flexible OTFTs, the devices were cyclically bent up to $10^5$ times with 5mm bending radius. In the most of the devices after $10^5$ times of bending cycles, the off-current of the OTFT with no encapsulation layers was quickly increased due to increases in the conductivity of the pentacene caused by doping effects from $O_2$ and $H_2O$ in the atmosphere, which leads to decrease in the $I_{on}/I_{off}$ and increase in the hysteresis. With encapsulation layers, however, the electrical stabilities of the OTFTs were improved significantly. In particular, the OTFTs with multi-stack hybrid encapsulation layer showed the best electrical stabilities up to the bending cycles of $10^5$ times compared to the devices with single organic encapsulation layer. Changes in electrical properties of cyclically bent OTFTs with encapsulation layers will be discussed in detail.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.2
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• pp.295-300
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• 2007

High temperature superconducting (HTS) windings for an HTS transformer which have been developed have two kinds of type, one is the layer winding and the other is disk winding. The layer winding has adopted for an HTS power transformer so far because of the small AC losses of the HTS windings. The disk windings have surface of the HTS wire. We propose a new winding method for a high voltage HTS transformer which has advantages of both type of HTS windings, and we call it continuous disk winding. This new HTS winding consists of pile of HTS disk windings. The continuous disk winding was fabricated with multi-stacked HTS wires for dover HTS transformer. We can check the potential possibility from the characteristic test of the fabricated winding. The new type HTS windings can be applied to HTS power transformers, especially to the high voltage ones.