• IEIE Transactions on Smart Processing and Computing
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• 제5권5호
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• pp.331-336
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• 2016

Multi-bit tries have been proposed to improve the search performance of a binary trie by providing flexibility in stride values, which identify the number of bits examined at a time. However, constructing a variable-stride multi-bit trie is challenging since it is not easy to determine a proper stride value that satisfies the required performance at each node. The aim of this paper is to identify several desired characteristics of a trie for IP address lookup problems, and to propose a multi-stride decision trie that has these characteristics. Simulation results using actual routing sets with about 30,000 to 220,000 prefixes show that the proposed multi-stride decision trie has the desired characteristics and achieves IP address lookup using 33% to 47% of the 2-bit trie in the average number of node accesses, while requiring a smaller amount of memory.

• Progress in Superconductivity
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• 제7권2호
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• pp.109-113
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• 2006

The Arithmetic Logic Unit (ALU) is a core element of a computer processor that performs arithmetic and logic operations on the operands in computer instruction words. We have developed and tested an RSFQ multi-bit ALU constructed with half adder unit cells. To reduce the complexity of the ALU, We used half adder unit cells. The unit cells were constructed of one half adder and three de switches. The timing problem in the complex circuits has been a very important issue. We have calculated the delay time of all components in the circuit by using Josephson circuit simulation tools of XIC, $WRspice^{TM}$, and Julia. To make the circuit work faster, we used a forward clocking scheme. This required a careful design of timing between clock and data pulses in ALU. The designed ALU had limited operation functions of OR, AND, XOR, and ADD. It had a pipeline structure. The fabricated 1-bit, 2-bit, and 4-bit ALU circuits were tested at a few kilo-hertz clock frequency as well as a few tens giga-hertz clock frequency, respectively. For high-speed tests, we used an eye-diagram technique. Our 4-bit ALU operated correctly at up to 5 GHz clock frequency.

• 전자공학회논문지B
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• 제33B권4호
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• pp.209-216
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• 1996

In this paper, we propose a learning method of multi-layer perceptrons (MLPs) with 8-bit data precision. The suggested method uses the cross-entropy cost function to remove the slope term of error signal in output layer. To decrease the possibility of overflows, we use 16-bit weighted sum results into the 8-bit data with appropriate range. In the forwared propagation, the range for bit-conversion is determined using the saturation property of sigmoid function. In the backwared propagation, the range for bit-conversion is derived using the probability density function of back-propagated signal. In a simulation study to classify hadwritten digits in the CEDAR database, our method shows similar generalization performance to the error back-propagation learning with 16-bit precision.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.921-926
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• 2003

This paper describes a new type of the spatial filter detector (SFD) with variable and multi-valued weighting function. This SFD called variable spatial filter detector with multi-valued weighting function (VSFDwMWF) uses current-mode circuits for noise resistance and high-resolution weighting values. Total weighting values consist of 7bit, 6-signal bit and 1-sign bit. We fabricate VSFDwMWF chip using Rohm 0.35${\mu}$m CMOS process. VSFDwMWF chip includes two-dimensional 10${\times}$13 photodiode array and current-mode weighting control circuit. Simulation shows the weighting values are varied and multi-valued by external switching operation. The layout of VSFDwMWF chip is shown.

• 한국전기전자재료학회논문지
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• 제18권3호
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• pp.193-198
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• 2005

NOR type flash 32 ${\times}$ 32 way are fabricated by using the typical 0.35 ${\mu}{\textrm}{m}$ CMOS process. The structure of array is the NOR type with common source line. In this paper, optimized program and erase voltage conditions are presented to realize multi-bit per cell at the CSL-NOR array. These are considered selectivity of selected bit and disturbances of unselected bits. Retention characteristics of locally trapped-charges in the nitride layer are investigated. The lateral diffusion and vertical detrapping to the tunneling oxide of locally trapped charges as a function of retention time are investigated by using the charge pumping method. The results are directly shown by change of the trapped-charges quantities.

• 한국전자거래학회지
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• 제11권2호
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• pp.1-11
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• 2006

본 논문에서는 멀티 쉬프팅 기법을 이용한 효율적인 유한체의 역수 연산 알고리즘을 제안하고 있다. 연산 알고리즘의 효율성은 사용하는 기저에 따라 영향이 있음이 많은 선행 연구를 통해 알려져 왔으며, 보편적으로 다항식 기저와 최적 다항식 기저를 사용하여 연구하였다. 본 연구에서는 몽고메리 알고리즘에 바탕을 둔 멀티비트 쉬프팅 기법을 수정하고 구현하였다. 역수 연산을 수행하기 위해 본 연구에서 사용한 기약 다항식타입은 AOP와 3항식 이며, 수행 결과 26%까지의 성능향상을 보였다. 본 논문에서 제안한 알고리즘은 구현이 쉽고, 다양한 분야에서 응용이 가능하다.

• Journal of electromagnetic engineering and science
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• 제10권2호
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• pp.50-55
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• 2010

Orthogonal Frequency Division Multiplexing(OFDM) dual-hop systems can take full advantages of the techniques of both multi-hop communication and OFDM. To achievethis end, we propose a joint subcarrier matching, power allocation and bit loading algorithm operating under a total power constraint and the same Bit Error Rate(BER) threshold over all subcarriers. Simulation results demonstrated system throughput improvement compared to single-hop systems and dual-hop systems with different bit loading algorithms for each relay position, power constraint, and required BER.

• Journal of Communications and Networks
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• 제12권5호
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• pp.475-479
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• 2010

The clipping value, defined as the log-likelihood ratio (LLR) in the case wherein all the list of candidates have the same binary value, is investigated, and an effective method to estimate it is presented for iterative tree search detection. The basic principle behind the method is that the clipping value of a channel bit is equal to the LLR of the maximum probability of correct decision of the bit to the corresponding probability of erroneous decision. In conjunction with multilevel bit mappings, the clipping value can be calculated with the parameters of the number of transmit antennas, $N_t$; number of bits per constellation point, $M_c$; and variance of the channel noise, $\sigma^2$, per real dimension in the Rayleigh fading channel. Analyses and simulations show that the bit error performance of the proposed method is better than that of the conventional fixed-value method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(1)
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• pp.89-92
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• 2001

In this paper, adaptive multi-stage parallel interference cancellation (PIC) receiver is considered for a multi-rate DS-CDMA system. In each stage of the adaptive multi-stage PIC receiver, multiple access interference (MAI) estimates are obtained using the sub-bit estimates from the Previous stage and the adaptive weights for the sub-bit estimates. The adaptive weights are obtained by minimizing the mean squared error between the received signal and its estimate through a least mean square (LMS) algorithm. It is shown that the adaptive multi- stage PIC receiver achieves smaller BER than the matched filter receiver, multi-stage PIC receiver, and multi-stage partial PIC receiver for the multi-rate DS-CDMA system in a Rayleigh fading channel.

• 사물인터넷융복합논문지
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• 제9권3호
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• pp.81-86
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• 2023

플래시 메모리 기반 저장장치인 SSD(solid state disk)는 높은 집적도와 빠른 데이터 처리가 가능한 장점을 가지고 있다. 따라서 급격하게 증가하고 있는 빅데이터를 관리하는 고용량 데이터 저장 시스템의 저장장치로 활용되고 있다. 그러나 저장 미디어인 플래시 메모리에 일정 횟수 이상 반복해서 쓰기/지우기 동작을 반복하면 셀이 마모되어 사용하지 못하는 물리적 한계가 있다. 본 논문에서는 플래시 메모리의 불량률을 줄이고 수명을 연장하기 위해 불량이 발생한 다중 비트 셀을 단일 비트 셀로 변환하여 사용하는 방법을 제안한다. 제안하는 아이디어는 물리적 특징이 다르지만 동일하게 불량으로 처리되고 있는 다중 비트 셀과 단일 비트 셀의 불량 및 처리 방법을 구분하였다. 그리고 불량이 예상되는 다중 비트 셀을 단일 비트 셀로 변환하여 불량률을 개선하고 전체적인 수명을 연장하였다. 마지막으로 시뮬레이션을 통해 SSD의 증가한 수명을 측정하여 제안하는 아이디어의 효과를 증명하였다.