• 전기의세계
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• v.29 no.2
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• pp.111-117
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• 1980

Contacts formed by vacuum evaporation of As-Te-Si-Ge chalcogenide glass onto Al metal (99.9999%) are studied by measuring paralle capacitance C(V), Cp(w), resistance R(V), Rp(w), and I-V characteristics. The fact that contact metal alloying produced high-resistance region is confirmed from the measurements of parallel capacitance and resistance. From the I-V characteristics in the pre-switcing region, it is found that electronic conduction and sitching occurs in the vicinity of metal-amorphous semiconductor interface. From the experimental obsevations, it is concuded that the current flow in the thin film is space-charge limited current (SCLC) due to the tunneling of electrons through the energy barriers.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• Journal of the Optical Society of Korea
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• v.20 no.1
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• pp.130-134
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• 2016

The influence of Au/Ni-based contact formed on a lightly-doped (7.3×1017cm−3, Zn-doped) InGaAsP layer for electrical compensation of surface plasmon polariton (SPP) propagation under various rapid thermal annealing (RTA) conditions has been studied. The active control of SPP propagation is realized by electrically pumping the InGaAsP multiple quantum wells (MQWs) beneath the metal planar waveguide. The metal planar film acts as the electric contact layer and SPP waveguide, simultaneously. The RTA process can lower the metal-semiconductor electric contact resistance. Nevertheless, it inevitably increases the contact interface morphological roughness, which is detrimental to SPP propagation. Based on this dilemma, in this work we focus on studying the influence of RTA conditions on electrical control of SPPs. The experimental results indicate that there is obvious degradation of electrical pumping compensation for SPP propagation loss in the devices annealed at 400℃ compared to those with no annealing treatment. With increasing annealing duration time, more significant degradation of the active performance is observed even under sufficient current injection. When the annealing temperature is set at 400℃ and the duration time approaches 60s, the SPP propagation is nearly no longer supported as the waveguide surface morphology is severely changed. It seems that eutectic mixture stemming from the RTA process significantly increases the metal film roughness and interferes with the SPP signal propagation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.1
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• pp.20-30
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• 2001

A 1.8V $650{\;}\textrm{mm}^2$ 4Gb DRAM having $0.10{\;}\mu\textrm{m}^2$ cell size has been successfully developed using 0.11 $\mu\textrm{m}$DRAM technology. Considering manufactur-ability, we have focused on developing patterning technology using KrF lithography that makes $0.11{\;}\mu\textrm{m}$ DRAM technology possible. Furthermore, we developed novel DRAM technologies, which will have strong influence on the future DRAM integration. These are novel oxide gap-filling, W-bit line with stud contact for borderless metal contact, line-type storage node self-aligned contact (SAC), mechanically stable metal-insulator-silicon (MIS) capacitor and CVD Al process for metal inter-connections. In addition, 80 nm array transistor and sub-80 nm memory cell contact are also developed for high functional yield as well as chip performance. Many issues which large sized chip often faces are solved by novel design approaches such as skew minimizing technique, gain control pre-sensing scheme and bit line calibration scheme.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1139-1141
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• 2006

For the bottom-contact pentacene organic thin-film transistors (OTFTs), the insertion of a thin PMMA layer $(20{\AA})$ between the pentacene and the electrode improves the electrical performances, such as carrier mobility and on-current magnitude, about 4 times larger than those of the devices without the PMMA. The performance enhancement is presumably due to the decreased contact resistance between metal and pentacene by inserting the thin PMMA layer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.187-187
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• 2007

This paper presents the electrical properties of SiGe HBTs designed with bottom collector and single metal layer structure for RF power amplifier. Base layer was formed with graded-SiGe/Si structures and the collector place to the bottom of the device. Bottom collector and single metal layer structures could significantly simplify the fabrication process. We studied about the influence of SiGe base thickness, number of emitter fingers and temperature dependence (< $200^{\circ}C$) on electrical properties. The feasible application in 1~2GHz frequency from measured data $BV_{CEO}$ ~10V, $f_r$~14 GHz, ${\beta\simeq}110$, NF~1 dB using packaged SiGe HBTs. We will discuss the temperature dependent current flow through the e-b, b-c junctions to understand stability and performance of the device.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.935-936
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• 2009

In this paper, we describe the basic operating mechanism of our novel reflective display, Fast Moving Ball Actuator (FMBA) mode[1], using micro-sized metal coated polymer ball in fluid medium. Metal surface of the ball can be charged up by contact electrode and their locations can be controlled by applied field to obtain optically on and off state. In the medium with high viscosity, the response speed of the moving ball might be reached into their terminal velocity and changed in proportion to the frequency of applied voltage on the electrodes.

• Journal of the Semiconductor & Display Technology
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• v.17 no.4
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• pp.66-69
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• 2018

This study was researched the electrical properties of semiconductor devices such as ITO, $SiO_2$, $V_2O_5$ thin films. The films of ITO, $SiO_2$, $V_2O_5$ were deposited by the rf magnetron sputtering system with mixed gases of oxygen and argon to generate the plasma. All samples were cleaned before deposition and prepared the metal electrodes to research the current-voltage properties. The electrical characteristics of semiconductors depends on the interface's properties at the junction. There are two kinds of junctions such as ohmic and schottky contacts in the semiconductors. In this study, the ITO thin film was shown the ohmic contact properties as the linear current-voltage curves, and the electrical characteristics of $SiO_2$ and $V_2O_5$ films were shown the non-linear current-voltage curves as the schottky contacts. It was confirmed that the electronic system with schottky contacts enhanced the electronic flow owing to the increment of efficiency and increased the conductivity. The schottky contact was only defined special characteristics at the semiconductor and the interface depletion layer at the junction made the schottky contact which has the effect of leakage current cutoff. Consequently the semiconductor device with shottky contact increased the electronic current flow, in spite of depletion of carriers.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.5
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• pp.276-283
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• 2017

A polysilicon-based metal-semiconductor-metal (MSM) photodetector was fabricated by means of our new methods. Its photoresponse characteristics were analyzed to see if it could be applied to a sensor system. The processes on which this study focused were an alloy-annealing process to form metal-polysilicon contacts, a post-annealing process for better light absorption of as-deposited polysilicon, and a passivation process for lowering defect density in polysilicon. When the alloy annealing was achieved at about $400^{\circ}C$, metal-polysilicon Schottky contacts sustained a stable potential barrier, decreasing the dark current. For better surface morphology of polysilicon, rapid thermal annealing (RTA) or furnace annealing at around $900^{\circ}C$ was suitable as a post-annealing process, because it supplied polysilicon layers with a smoother surface and a proper grain size for photon absorption. For the passivation of defects in polysilicon, hydrogen-ion implantation was chosen, because it is easy to implant hydrogen into the polysilicon. MSM photodetectors based on the suggested processes showed a higher sensitivity for photocurrent detection and a stable Schottky contact barrier to lower the dark current and are therefore applicable to sensor systems.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.352-354
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• 1995

The optical and electrical properties of High Speed AlGaAs infrared LED by using metal wet etch process instead of metal lift-off process are investigated. The power out increases when metal contact is patterned by wet etch process. Forward voltage and Reverse voltage for metal wet etch process represent higher value than the metal lift-off process. The aging effect of power out also indicates good results with wet etch process. The wet etch process for metal contact reveals reliable LED device properties.