JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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Performance Optimization Study of FinFETs Considering Parasitic Capacitance and Resistance

  • An, TaeYoon (Department of Semiconductor Systems Engineering, College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Choe, KyeongKeun (Department of Semiconductor Systems Engineering, College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kwon, Kee-Won (Department of Semiconductor Systems Engineering, College of Information and Communication Engineering, Sungkyunkwan University) ;
  • Kim, SoYoung (Department of Semiconductor Systems Engineering, College of Information and Communication Engineering, Sungkyunkwan University)
  • Received : 2014.05.07
  • Accepted : 2014.07.28
  • Published : 2014.10.30
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Abstract

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

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