• Journal of Sensor Science and Technology
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• v.31 no.3
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• pp.151-155
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• 2022

In this paper, we present a highly-sensitive gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector using multi-finger structure whose photocurrent increases in proportion to the number of fingers. The drain current that flows through a MOSFET using multi-finger structure is proportional to the number of fingers. This study intends to confirm that the photocurrent of a GBT MOSFET-type photodetector that uses the proposed multi-finger structure is larger than the photocurrent per unit area of the existing GBT MOSFET-type photodetectors. Analysis and measurement of a GBT MOSFET-type photodetector that utilizes a multi-finger structure confirmed that photocurrent increases in ratio to the number of fingers. In addition, the characteristics of the photocurrent in relation to the optical power were measured. In order to determine the influence of the incident the wavelength of light, the photocurrent was recorded as the incident the wavelength of light varied over a range of 405 to 980 nm. A highly-sensitive GBT MOSFET-type photodetector with multi-finger structure was designed and fabricated by using the Taiwan semiconductor manufacturing company (TSMC) complementary metal-oxide-semiconductor (CMOS) 0.18 um 1-poly 6-metal process and its characteristics have been measured.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.383-389
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• 2001

We report on the design, fabrication, and characterization of 0.35${\mu}{\textrm}{m}$-gate AIGaAs/InGaAs PHEMTs for millimeter-wane applications. The epi-wafer structures were designed using ATLAS for optimum DC and AC characteristics, 0.351m-gate AIGaAs/rnGaAs PHEMTs having different gate widths and number of fingers were fabricated using electron beam lithography Dependence of RF characteristics of PHEMT on gate finger with and number of gate fingers have been investigated. PHEMT haying two 0.35$\times$60${\mu}{\textrm}{m}$$^2$ gate fingers showed the knee voltage, pinch-off voltage, drain saturation current density, and maximum transconductance of 1.2V, -1.5V, 275㎃/mm, and 260.17㎳/mm, respectively. The PHEMT showed fT(equation omitted)(current gain cut-off frequency) of 45㎓ and fmax(maximum oscillation frequency) of 100㎓. S$_{21}$ and MAG of the PHEMT were 3.6dB and 11.15dB, respectively, at 35㎓

• Journal of electromagnetic engineering and science
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• v.13 no.2
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• pp.127-133
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• 2013

We examined the scaling effects of a number of gate_fingers (N) and gate_widths (w) on the high-frequency characteristics of $0.1-{\mu}m$ metamorphic high-electron-mobility transistors. Functional relationships of the extracted small-signal parameters with total gate widths ($w_t$) of different N were proposed. The cut-off frequency ($f_T$) showed an almost independent relationship with $w_t$; however, the maximum frequency of oscillation ($f_{max}$) exhibited a strong functional relationship of gate-resistance ($R_g$) influenced by both N and $w_t$. A greater $w_t$ produced a higher $f_{max}$; but, to maximize $f_{max}$ at a given $w_t$, to increase N was more efficient than to increase the single gate_width.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.84-87
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• 2000

In this paper, a high gain-broad bandwidth MMIC distributed amplifier was designed using cascaded single section distributed amplifier configuration. The PHEMT for this studies was fabricated at our lab The PHEMT has a 0.2 $\mu\textrm{m}$ gate length. a 80 $\mu\textrm{m}$ unit gate width and 4 gate fingers. A designed MMIC amplifier have higher S$\sub$21/ gain than the common distributed amplifier using the same number of active devices. From the simulated result, we obtained that the S$\sub$21/ gain of DC ∼ 20 GHz bandwidth was 15.6 dB and flatness was ${\pm}$0.9 dB, and input and output reflection coefficient were lower than -8 dB. The simulated gain shows an improvement 7.3 dB compared with those of conventional distributed amplifier. And the chip size is 2.0 ${\times}$ 1.2 $\textrm{mm}^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.525-536
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• 2014

Recently, the first generation of mass production of FinFET-based microprocessors has begun, and scaling of FinFET transistors is ongoing. Traditional capacitance and resistance models cannot be applied to nonplanar-gate transistors like FinFETs. Although scaling of nanoscale FinFETs may alleviate electrostatic limitations, parasitic capacitances and resistances increase owing to the increasing proximity of the source/drain (S/D) region and metal contact. In this paper, we develop analytical models of parasitic components of FinFETs that employ the raised source/drain structure and metal contact. The accuracy of the proposed model is verified with the results of a 3-D field solver, Raphael. We also investigate the effects of layout changes on the parasitic components and the current-gain cutoff frequency ($f_T$). The optimal FinFET layout design for RF performance is predicted using the proposed analytical models. The proposed analytical model can be implemented as a compact model for accurate circuit simulations.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.12-15
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• 2000

In this paper, we have fabricated the PHEMT's with AlGaAs/InGaAs/GaAs and measured characteristics of DC and frequencies. The PHEMT's has a 0.35$\mu\textrm{m}$ gate length, gate width of 60$\mu\textrm{m}$ and 80$\mu\textrm{m}$, and fingers of 2 and 4. From the measurements results for the 60$\mu\textrm{m}$ ${\times}$ 2 PHEMT's, we obtained 1.2V of Vk, -3.5V of Vp, 46mA of Idss, 221mS/mmof gm, and 3.6dB of S$\sub$21/ gain, 45GHz of f$\sub$T,/ 100GHz of fmax. And, in case of 80$\mu\textrm{m}$ ${\times}$ 4 PHEMT's, we obtained 1.2V of Vk, -4.5V of Vp, 125mA of Idss, 198mS/mm of gm, and 2.0dB of S$\sub$21/ gain. 44GHz of f$\sub$T/, 70GHz of fmax at 35GHz frequency. Also, MAG are decreased as a number of finger are Increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.1
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• pp.30-36
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• 2001

0.35 ${\mu}{\textrm}{m}$-gate AlGaAs/InGaAs PHEMTs have been fabricated using electron beam lithography. DC and AC characteristics of PHEMTs having different gate widths and number of fingers were measured at various bias conditions. An MIMIC power amplifier operating at 35 GHz has been designed and fabricated using passive element library. The power amplifier showed gain and input reflection coefficient of 7.9 ㏈ and -15 ㏈, respectively, at 27.6 GHz.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.245-248
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• 2011

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).