• Proceeding of EDISON Challenge
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• 2016.03a
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• pp.362-364
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• 2016

본 논문에서는 MOS(Metal Oxide Semiconductor) Capacitor의 산화막내에 다양한 원인에 의해 존재하는 비이상적인 전하들 중 Fixed Oxide Charge가 소자의 문턱전압에 어떤 영향을 주는지 분석했다. 분석한 결과 n+ polysilicon Gate를 가지고, 산화막인 $SiO_2$의 두께가 3nm이고, 도핑농도가 $10^{18}cm^{-2}$인 P형 실리콘 기판으로 이루어진 MOS Capacitor에서 Fixed Oxide Charge Density가 $C/cm^2$ 이상일 때 문턱전압을 0.01V 이상 감소시키고 $C/cm^2$ 이하일 때 문턱전압을 0.01V 이상 증가시켰다.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.64.4-64
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• 1998

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.45-46
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• 2009

We have fabricated advanced metal-oxide-semiconductor (MOS) capacitors with thin (${\approx}10\;nm$) Inductive-Coupled Plasma (ICP) CVD $Si_xN_y$ dielectric layers and investigated electrical properties of nitrided $SiO_2$/4H-SiC interface after oxidizing the $Si_xN_y$ in dry oxidation and/or $N_2$ annealing. An improvement of electrical properties have been revealed in capacitance-voltage (C-V) and current density-electrical field (J-E) measurements if compared with non-annealed oxidized-SiN. The improvements of SiC MOS capacitors formed by oxidized-SiN have been explained in this paper.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.333-335
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• 1997

This paper was performed to investigate the characteristic of the Pt-MIS(Metal Insulator Semiconductor) capacitor composed of the LPCVD nitride on the oxide for the hydrogen gas detection. Pt was used as catalytic metal for detecting the hydrogen gas and the flat band voltage shift was measured at various hydrogen concentration and catalytic metal thickness. We found the flat band voltage shift was proportional to the hydrogen concentration and catalytic metal thickness was little effect to the response time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1997.11a
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• pp.25-29
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• 1997

Capacitor-type MONOS (metal-oxide-nitride-oxide- semiconductor) NVSMs with 23$\AA$ tunneling oxide and 40$\AA$ blocking oxide were fabricated. The thicknesses of nitride layer were 45$\AA$, 91$\AA$ and 223$\AA$, Breakdown characteristics of MONOS devices were measured to investigate the reliability of superthin ONO structure using ramp voltage and constant voltage method. Reducing the nitride thickness will significantly increase the reliablity of MONOS NVSM.

• Journal of the Korean Ceramic Society
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• v.38 no.10
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• Transactions on Electrical and Electronic Materials
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• v.12 no.1
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• pp.35-39
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• 2011

An electrically erasable programmable read-only memory (EEPROM) containing a stacked metal-insulator-metal (MIM) and n-well capacitor is proposed. It was fabricated using a 0.18 $\mu$m standard complementary metal-oxide semiconductor process. The depletion capacitance of the n-well region was effectively applied without sacrificing the cell-area and control gate coupling ratio. The device performed very similarly to the MIM capacitor cell regardless of the smaller cell area. This is attributed to the high control gate coupling ratio and capacitance. The erase speed of the proposed EEPROM was faster than that of the cell containing the MIM control gate.