• 제목/요약/키워드: Metal-insulator-semiconductor

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게이트 절연막에 의한 다이아몬드 MIS (Metal-Insulator-Semiconductor) 계면의 전기적 특성 개선과 전계효과 트랜지스터에의 응용 (Improvement of Electrical Properties of Diamond MIS (Metal-Insulator- Semiconductor) Interface by Gate Insulator and Application to Metal-Insulator- Semiconductor Field Effect Transistors)

  • 윤영
    • 한국전자파학회논문지
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    • 제14권6호
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    • pp.648-654
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    • 2003
  • 본 논문에서는 비 산화물인 불소화합물 게이트절면막을 이용하여 박막반도체 다이아몬드 MS계면(Metal-Insulator-Semiconductor Interface)의 전기적 안정화를 실현하였다. 특히 산소 게터링 효과(Oxygen-Gettering Effect)에 의한 표면준위 억제를 통해, 박막반도체 다이아몬드 MIS계면에 있어서 최적의 전기적 특성을 부여하는 BiF2 게이트절연막을 개발하였다. 본 논문의 결과에 의하면, BaF$_2$ 게이트 절연막을 이용하여 제작한 A1/BaF2/diamond MIS 다이오드와 MISFET(Metal-Insulator-Semiconductor Field Effect Transistor)로부터 저농도의 ~10101/$\textrm{cm}^2$ eV의 표면준위밀도가 관측되었고, 그리고 이제까지 발표된 다이아몬드 박막반도_체 FET중 최고치인 400 $\textrm{cm}^2$/Vs의 유효이동도가 관찰되었다.

Effect of Bottom Electrode on Resistive Switching Voltages in Ag-Based Electrochemical Metallization Memory Device

  • Kim, Sungjun;Cho, Seongjae;Park, Byung-Gook
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권2호
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    • pp.147-152
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    • 2016
  • In this study, we fabricated Ag-based electrochemical metallization memory devices which is also called conductive-bridge random-access memory (CBRAM) in order to investigate the resistive switching behavior depending on the bottom electrode (BE). RRAM cells of two different layer configurations having $Ag/Si_3N_4/TiN$ and $Ag/Si_3N_4/p^+$ Si are studied for metal-insulator-metal (MIM) and metal-insulator-silicon (MIS) structures, respectively. Switching voltages including forming/set/reset are lower for MIM than for MIS structure. It is found that the workfunction different affects the performances.

저온공정 n-InGaAs Schottky 접합의 구조적 특성 (Structural Analysis of Low Temperature Processed Schottky Contacts to n-InGaAs)

  • 이홍주
    • 한국전기전자재료학회논문지
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    • 제14권7호
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    • pp.533-538
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    • 2001
  • The barrier height is found to increase from 0.25 to 0.690 eV for Schottky contacts on n-InGaAs using deposition of Ag on a substrate cooled to 77K(LT). Surface analysis leads to an interface model for the LT diode in which there are oxide compounds of In:O and As:O between the metal and semiconductor, leading to behavior as a metal-insulator-semiconductor diode. The metal film deposited t LT has a finer and more uniform structure, as revealed by scanning electron microscopy and in situ metal layer resistance measurement. This increased uniformity is an additional reason for the barrier height improvement. In contrast, the diodes formed at room temperature exhibit poorer performance due to an unpassivated surface and non-uniform metal coverage on a microscopic level.

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Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

  • Gupta, Ritesh;Kaur, Ravneet;Aggarwal, Sandeep Kr;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제10권1호
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    • pp.66-77
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    • 2010
  • Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

OTFT용 용액공정의 에틸렌-브리지드 실세스퀴옥산 게이트 절연체 (Solution-Processed Gate Insulator of Ethylene-Bridged Silsesquioxnae for Organic Field-Effect Transistor)

  • 이덕희;정현담
    • 통합자연과학논문집
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    • 제3권1호
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    • pp.7-18
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    • 2010
  • Ethylene-bridged silsesquioxane resins were synthesized from two monomers: 1,2-bis(trimethoxysilyl)ethane and methyltrimethoxysilane. The silsesquioxane thin films were spin-coated from the copolymerized resins on silicon wafer. Metal insulator metal (MIM), metal insulator semiconductor (MIS) devices were utilized to investigate the electrical properties of the copolymerized thin films. As the films were inserted as gate insulator in the OTFT devices, the field effect mobilitites were evaluated by employing Poly(3-hexylthiophene) (P3HT) as organic semiconductor, which shows that their dielectric properties and mobility values are dependent on the molecular structures and Si-OH concentration involving in the films.

강유전체 PZT박막을 이용한 MFMIS소자의 모델링 및 특성에 관한 시뮬레이션 연구 (Computer Modeling and characteristics of MFMIS devices Using Ferroelectric PZT Thin Film)

  • 국상호;박지온;문병무
    • 한국전기전자재료학회논문지
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    • 제13권3호
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    • pp.200-205
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    • 2000
  • This paper describes the structure modeling and operation characteristics of MFMIS(metal-ferroelectric-metal-insulator-semiconductor) device using the Tsuprem4 which is a semiconductor device tool by Avanti. MFMIS device is being studied for nonvolatile memory application at various semiconductor laboratory but it is difficult to fabricate and analyze MFMIS devices using the semiconductor simulation tool: Tsuprem4, medici and etc. So the new library and new materials parameters for adjusting ferroelectric material and platinum electrodes in the tools are studied. In this paper structural model and operation characteristics of MFMIS devices are measured, which can be easily adopted to analysis of MFMIS device for nonvolatile memory device application.

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Short Channel Analytical Model for High Electron Mobility Transistor to Obtain Higher Cut-Off Frequency Maintaining the Reliability of the Device

  • Gupta, Ritesh;Aggarwal, Sandeep Kumar;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제7권2호
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    • pp.120-131
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    • 2007
  • A comprehensive short channel analytical model has been proposed for High Electron Mobility Transistor (HEMT) to obtain higher cut-off frequency maintaining the reliability of the device. The model has been proposed to consider generalized doping variation in the directions perpendicular to and along the channel. The effect of field plates and different gate-insulator geometry (T-gate, etc) have been considered by dividing the area between gate and the high band gap semiconductor into different regions along the channel having different insulator and metal combinations of different thicknesses and work function with the possibility that metal is in direct contact with the high band gap semiconductor. The variation obtained by gate-insulator geometry and field plates in the field and channel potential can be produced by varying doping concentration, metal work-function and gate-stack structures along the channel. The results so obtained for normal device structure have been compared with previous proposed model and numerical method (finite difference method) to prove the validity of the model.

Analytical Model for Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) for its High Frequency and High Power Applications

  • Gupta, Ritesh;Aggarwal, Sandeep Kr;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권3호
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    • pp.189-198
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    • 2006
  • A new analytical model has been proposed for predicting the sheet carrier density of Metal insulator Semiconductor High Electron Mobility Transistor (MISHEMT). The model takes into account the non-linear relationship between sheet carrier density and quasi Fermi energy level to consider the quantum effects and to validate it from subthreshold region to high conduction region. Then model has been formulated in such a way that it is applicable to MESFET/HEMT/MISFET with few adjustable parameters. The model can also be used to evaluate the characteristics for different gate insulator geometries like T-gate etc. The model has been extended to forecast the drain current, conductance and high frequency performance. The results so obtained from the analysis show excellent agreement with previous models and simulated results that proves the validity of our model.