• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.1-7
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• 2013

In this paper, a biosensor based on a gated lateral bipolar junction transistor (BJT) is proposed. The gated lateral BJT can function as both a metal-oxide-semiconductor field-effect transistor (MOSFET) and a BJT. By using the self-assembled monolayer (SAM) method, the C-reactive protein antibodies were immobilized on the floating gate of the device as the sensing membrane. Through the experiments, the characteristics of the biosensor were analyzed in this study. According to the results, it is indicated that the gated lateral BJT device can be successfully applied as a biosensor. Additionally, we found that the sensitivity of the gated lateral BJT can be varied by adjusting the emitter (source) bias.

• Journal of electromagnetic engineering and science
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• 제14권4호
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• pp.411-414
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• 2014

A switch is one of the most useful circuits for controlling the path of signal transmission. It can be added to digital circuits to create a kind of gate-level device and it can also save information into memory. In RF subsystems, a switch is used in a different way than its general role in digital circuits. The most important characteristic to consider when designing an RF switch is keeping the isolation as high as possible while also keeping insertion loss as low as possible. For high isolation, we propose leakage signal cancellation and inductive switching for designing a singlepole double-throw (SPDT) RF switch. By using the proposed method, an isolation level of more than 23 dB can be achieved. Furthermore, the heterojunction bipolar transistor (HBT) process is used in the RF switch design to keep the insertion loss low. It is demonstrated that the proposed RF switch has an insertion loss of less than 2 dB. The RF switch operates from 1 to 8 GHz based on the $0.18-{\mu}m$ SiGe HBT process, taking up an area of $0.3mm^2$.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.134-135
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• 2008

Ultra-thin $SiO_2/ZrO_2$ dielectrics were deposited by atomic layer chemical vapor deposition (ALCVD) method for non-volatile memory application. Metal-oxide-semiconductor (MOS) capacitors were fabricated by stacking ultra-thin $SiO_2$ and $ZrO_2$ dielectrics. It is found that the tunneling current through the stacked dielectric at the high voltage is lager than that through the conventional silicon oxide barrier. On the other hand, the tunneling leakage current at low voltages is suppressed. Therefore, the use of ultra-thin $SiO_2/ZrO_2$ dielectrics as a tunneling barrier is promising for the future high integrated non-volatile memory.

• 전력전자학회논문지
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• 제25권5호
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• pp.412-419
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• 2020

In this study, a 70 W buck converter using GaN metal-oxide-semiconductor field-effect transistor (MOSFET) is developed. This converter exhibits over 97 % efficiency, high power density, and 48 V-to-12 V/1.2 V/1 V (triple output). Three gate drivers and six GaN MOSFETs are placed in a 1 ㎠ area to enhance power density and heat dissipation capacity. The theoretical switching and conduction losses of the GaN MOSFETs are calculated. Inductances, capacitances, and resistances for the output filters of the three buck converters are determined to achieve the desired current, voltage ripples, and efficiency. An equivalent circuit model for the thermal analysis of the proposed triple-output buck converter is presented. The junction temperatures of the GaN MOSFETs are estimated using the thermal model. Circuit operation and temperature analysis are evaluated using a circuit simulation tool and the finite element analysis results. An experimental test bed is built to evaluate the proposed design. The estimated switch and heat sink temperatures coincide well with the measured results. The designed buck converter has 130 W/in³ power density and 97.6 % efficiency.

• ETRI Journal
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• 제38권1호
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• pp.133-140
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• 2016

This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

• Journal of Electrical Engineering and information Science
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• 제2권5호
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• pp.17-26
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• 1997

Interconnect characterization on a wafer level was performed. Test patterns for single, two-coupled, and triple-coupled lines ere designed by using 0.5$\mu\textrm{m}$ CMOS process. Then interconnect capacitances and resistances were experimentally extracted by using tow port network measurements, Particularly to eliminate parasitic effects, the Y-parameter de-embedding was performed with specially designed de-embedding patterns. Also, for the purpose of comparisons, capacitance matrices were calculated by using the existing CAD model and field-solver-based commercial simulator, METAL and MEDICI. This work experimentally verifies that existing CAD models or parameter extraction may have large deviation from real values. The signal transient simulation with the experimental data and other methodologies such as field-solver-based simulation and existing model was performed. as expected, the significantly affect on the signal delay and crosstalk. The signal delay due to interconnects dominates the sub-micron-based a gate delay (e.g., inverter). Particularly, coupling capacitance deviation is so large (about more than 45% in the worst case) that signal integrity cannot e guaranteed with the existing methodologies. The characterization methodologies of this paper can be very usefully employed for the signal integrity verification or he electrical design rule establishments of IC interconnects in the industry.

• 한국정보통신학회논문지
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• 제7권7호
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• pp.1369-1373
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• 2003

전력증폭기의 비선형성에 의해 채널간의 상호 변조 왜곡성분이 주로 발생하는 CDMA 시스템에서는 선형 전력증폭기가 요구된다. 본 논문에서는 평형 MESFET 전치왜곡 선형화기가 추가된 형태의 선형 전력증폭기를 통한 선형화 방법을 제안하였다. 제안된 선형화기는 한국 PCS주파수 대역에서 G1㏈가 12.1㏈이고 P1㏈가 30㏈m인 A급 전력증폭기에 연결하여 시뮬레이션 하였다. 종단전력증폭기에 1850MHz와 1851.23MHz의 2-tone 신호를 인가한 결과 3차 혼변조가 약 22㏈ 개선되었다.

• 한국전기전자재료학회논문지
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• 제30권8호
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• pp.479-483
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• 2017

The effect of $NH_3$ plasma treatment on device characteristics was confirmed for an optimized thin film transistor of poly-Si formed by ELA. When C-V curve was checked for MIS (metal-insulator-silicon), Dit of $NH_3$ plasma treated and MIS was $2.7{\times}10^{10}cm^{-2}eV^{-1}$. Also in the TFT device case, it was decreased to the sub-threshold slope of 0.5 V/decade, 1.9 V of threshold voltage and improved in $26cm^2V^{-1}S^{-1}$ of mobility. Si-N and Si-H bonding reduced dangling bonding to each interface. When gate bias stress was applied, the threshold voltage's shift value of $NH_3$ plasma treated device was 0.58 V for 1,000s, 1.14 V for 3,600s, 1.12 V for 7,200s. As we observe from this quality, electrical stability was also improved and $NH_3$ plasma treatment was considered effective for passivation.

• 한국정보통신학회논문지
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• 제6권1호
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• pp.103-108
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• 2002

MOSFET는 전력감소, 도핑농도 증가, 캐리어 속도 증가를 위해서 많은 변화를 가져왔다. 이러한 변화를 받아들이기 위해서, 채널의 길이와 공급전압이 감소해야만하며, 그것으로 인해 소자가 더욱 작아지게 되었다. 현존하고 있는 시뮬레이션 프로그램은 많은 기술자와 과학자들에 의해 개발되어졌다. 본 논문에서는 상용화되어지고 있는 두 가지 시뮬레이터인 Micro-tec과 ISE-TCAD을 사용하여 나노 구조 소자를 시뮬레이션하여 비교하였다. 소자의 게이트 길이(Lg)는 180nm를 사용하였다. 두 시뮬레이터를 사용하여 MOSFET의 특성과 I-V 곡선 및 전계에 대해서 비교 분석하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.743-746
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• 2000

Metal-ferroelectric-insulator-semiconductor(MFIS) devices using Pt/$LiNbO_3$/Si structure were successfully fabricated. The dielectric constant of the AIN film calculated from the capacitance in the accumulation region in the capacitance-voltage(C-V) curve was about 8.2. The gate leakage current density of MIS devices using a aluminum electrode showed the least value of 1$\times$$1O^{-8}$A/$cm^2$ order at the electric field of 500kV/cm. The dielectric constant of $LiNbO_3$film on AIN/Si structure was about 23 derived from 1MHz capacitance-voltage (C-V) measurement and the resistivity of the film at the field of 500kV/cm was about 5.6$\times$ $1O^{13}$ $\Omega$.cm.