• Title/Summary/Keyword: Memory Leakage

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Design of a High-Performance Match-Line Sense Amplifier for Selective Match-Line charging Technique (선택적 매치라인 충전기법에 사용되는 고성능 매치라인 감지 증폭기 설계)

  • Ji-Hoon Choi;Jeong-Beom Kim
    • The Journal of the Korea institute of electronic communication sciences
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    • v.18 no.5
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    • pp.769-776
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    • 2023
  • In this paper, we designed an MLSA(Match-line Sense Amplifier) for low-power CAM(Content Addressable Memory). By using the MLSA and precharge controller, we reduced power consumption during CAM operation by employing a selective match-line charging technique to mitigate power consumption caused by mismatch. Additionally, we further reduced power consumption due to leakage current by terminating precharge early when a mismatch occurs during the search operation. The designed circuit exhibited superior performance compared to the existing circuits, with a reduction of 6.92% and 23.30% in power consumption and propagation delay time, respectively. Moreover, it demonstrated a significant decrease of 29.92% and 52.31% in product-delay-product (PDP) and energy-delay-product (EDP). The proposed circuit was validated using SPECTRE simulation with TSMC 65nm CMOS process.

Optimized QCA SRAM cell and array in nanoscale based on multiplexer with energy and cost analysis

  • Moein Kianpour;Reza Sabbaghi-Nadooshan;Majid Mohammadi;Behzad Ebrahimi
    • Advances in nano research
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    • v.15 no.6
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    • pp.521-531
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    • 2023
  • Quantum-dot cellular automata (QCA) has shown great potential in the nanoscale regime as a replacement for CMOS technology. This work presents a specific approach to static random-access memory (SRAM) cell based on 2:1 multiplexer, 4-bit SRAM array, and 32-bit SRAM array in QCA. By utilizing the proposed SRAM array, a single-layer 16×32-bit SRAM with the read/write capability is presented using an optimized signal distribution network (SDN) crossover technique. In the present study, an extremely-optimized 2:1 multiplexer is proposed, which is used to implement an extremely-optimized SRAM cell. The results of simulation show the superiority of the proposed 2:1 multiplexer and SRAM cell. This study also provides a more efficient and accurate method for calculating QCA costs. The proposed extremely-optimized SRAM cell and SRAM arrays are advantageous in terms of complexity, delay, area, and QCA cost parameters in comparison with previous designs in QCA, CMOS, and FinFET technologies. Moreover, compared to previous designs in QCA and FinFET technologies, the proposed structure saves total energy consisting of overall energy consumption, switching energy dissipation, and leakage energy dissipation. The energy and structural analyses of the proposed scheme are performed in QCAPro and QCADesigner 2.0.3 tools. According to the simulation results and comparison with previous high-quality studies based on QCA and FinFET design approaches, the proposed SRAM reduces the overall energy consumption by 25%, occupies 33% smaller area, and requires 15% fewer cells. Moreover, the QCA cost is reduced by 35% compared to outstanding designs in the literature.

Thermally Stimulated Current Analysis of (Ba, Sr)TiO$_3$ Capacitor ((Ba, Sr)TiO$_3$ 커패시터의 Thermally Stimulated Current분석)

  • Kim, Yong-Ju;Cha, Seon-Yong;Lee, Hui-Cheol;Lee, Gi-Seon;Seo, Gwang-Seok
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.5
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    • pp.329-337
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    • 2001
  • It has been known that the leakage current in the low field region consists of the dielectric relaxation current and intrinsic leakage current, which cause the charge loss in dynamic random access memory (DRAM) storage capacitor using (Ba,Sr)TiO$_{3}$ (BST) thin film. Especially, the dielectric relaxation current should be seriously considered since its magnitude is much larger than that of the intrinsic leakage current in giga-bit DRAM operation voltage (~IY). In this study, thermally stimulated current (TSC) measurement was at first applied to investigate the activation energy of traps and relative evaluation of the density of traps according to process change. And, through comparing TSC to early methods of I-V or I-t measurement and analyzing, we identify the origin of the dielectric relaxation current and investigate the reliability of TSC measurement. First, the polarization condition such as electric field, time, temperature and heating rate was investigated for reliable TSC measurement. From the TSC measurement, the energy level of traps in the BST thin film has been investigated and evaluated to be 0.20($\pm$0.01) eV and 0.45($\pm$0.02) eV. Based on the TSC measurement results before and after rapid thermal annealing (RTA) process, oxygen vacancy is concluded to be the origin of the traps. TSC characteristics with thermal annealing in the MIM BST capacitor have shown the same trends with the current-voltage (I-V) and current-time (I-t) characteristics. This means that the TSC measurement is one of the effective methods to characterize the traps in the BST thin film.

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Electrical Properties of ReMnO3(Re:Y, Ho, Er) Thin Film Prepared by MOCVD Method (화학 기상 증착법으로 제조한 ReMnO3(Re:Y, Ho, Er) 박막의 전기적 특성)

  • Kim, Eung-Soo;Chae, Jung-Hoon;Kang, Seung-Gu
    • Journal of the Korean Ceramic Society
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    • v.39 no.12
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    • pp.1128-1132
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    • 2002
  • $ReMnO_3$(Re:Y, Ho, Er) thin films were prepared by MOCVD method available to non-volatile memory device with MFS-FET structure. $ReMnO_3$ thin films were deposited on the Si(100) substrate at 700${\circ}C$ for 2h. When the films were post-annealed at 900${\circ}C$ for 1h in air, the single phase of hexagonal $ReMnO_3$ thin films were detected. Ferroelectric properties of $ReMnO_3$ thin films were dependent on the degree of c-axis orientation in the single phase of hexagonal structure and remnant polarization (Pr) of $YMnO_3$ thin films with high degree of c-axis orientation was 105 nC/$cm^2$. Leakage current density was dependent on the grain size of microstructure and that of $YMnO_3$ thin films with grain size of 100∼150 nm was $10^{-8}$ A/$cm^2$ at applied voltage of 0.5 V.

A Study on Measures to Prevent Leakage of Process Fluid from the VCR Fitting used in the Semiconductor Manufacturing Process (반도체 제조 공정에서 사용되는 이송배관 연결부위(VCR Fitting)로부터 공정유체 누출사고 예방 대책에 관한 연구)

  • Dae Joon Lee;Sang Ryung Kim;Sang Gil Kim;Chung Sang Kang;Joon Won Lee
    • Journal of the Korean Institute of Gas
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    • v.27 no.2
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    • pp.79-85
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    • 2023
  • Recently, in the semiconductor process, large companies are seeking process changes from memory semiconductors to the foundry due to the increase in demand due to the 4th industry. industry is expanding. The characteristics of special gases and precursors, which are raw materials used to produce these semiconductor chips, are toxic, pyrophoric, inflammable, and corrosive. These semiconductor raw materials are operated in a closed system and do not leak to the outside during normal times, but when leaked, they spread to the inside of the gas box, and when proper ventilation is not provided inside the gas box, they spread to the outside, causing fires, explosions, or toxic substances. It can lead to major accidents such as leakage. Recently, there have been cases of accidents in which hazardous materials leaked from the closed system of the semi conductor process and spread to the inside and outside of the gas box. . In this study, we propose preventive measures based on the case of an accident in which raw material leaked from the VCR fitting, which is the connection part of the semiconductor raw material transfer pipe, and spread to the outside of the gas box.

The Effect of La Concentration on The PLZT(x/30/70) Thin Films for NVRAM Memory Device (비휘발성 메모리 소자를 위한 PLZT(x/30/70) 박막에 대한 La 농도변화의 효과)

  • 김성진;윤영섭
    • Proceedings of the IEEK Conference
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    • 2000.06b
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    • pp.28-31
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    • 2000
  • In this paper, the effects of La addition of PLZT(x/30/70) thin films Prepared by sol-gel method are investigated for NVFRAM application. The tetragonality (c/a), the grain size, and the surface roughness of PLZT thin films decrease with an increase of La concentration. As the La concentration increases, the dielectric constants at 10 kHz increase from 450 to 600, while the loss tangent decrease from 0.075 to 0.025. Also, the leakage current density at 100kV/cm decrease from 5.83$\times$10$^{-7}$ to 1.38$\times$10$^{-7}$ 4/$\textrm{cm}^2$. In the results of hysteresis loops measured at $\pm$170kV/cm, the remanent polarization and the coercive field of PLZT thin films with La concentration from 0 to 10㏖% decrease from 20.8 to 10.5 $\mu$C/cm and from 54.48 to 32.12kV/cm, respectively. After a fatigue measurement by applying 10$^{9}$ square pulses with $\pm$5V, the remanent polarizations of PLZT thin films with 0 and 10㏖% La concentration decrease about 64 and 42 % from initial state. In the results of retention measurement after 10$^{5}$ s, PLZT thin films with 0 to 10mo1% La concentration show that the remanent polarization is decreased about 43% and 9% from initial state, respectively.

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Effect of annealing pressure on the growth and electrical properties of $YMnO_3$ thin films deposited by MOCVD

  • Shin, Woong-Chul;Park, Kyu-Jeong;Yoon, Soon-Gil
    • Journal of Korean Vacuum Science & Technology
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    • v.4 no.1
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    • pp.6-10
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    • 2000
  • Ferroelectric YMnO$_3$ thin films were deposited on $Y_2$O$_3$/si(100) substrates by metalorganic chemical vapor deposition. The YMnO$_3$ thin films annealed in vacuum ambient (100 mTorr) above 75$0^{\circ}C$ show hexagonal structured YMnO$_3$. However, the film annealed in oxygen ambient shows poor crystallinity, and the second phase as $Y_2$O$_3$ and orthorhombic-YMnO$_3$ were shown. The annealing ambient and pressure on the crystallinity of YMnO$_3$ thin films is very important. The C-V characteristics have a hysteresis curve with a clockwise rotation, which indicates ferroelectric polarization switching behavior. When the gate voltage sweeps from +5 to 5 V, the memory window of the Pt/YMnO$_3$/Y$_2$O$_3$/Si gate capacitor annealed at 85$0^{\circ}C$ is 1.8 V. The typical leakage current densities of the films annealed in oxygen and vacuum ambient are about 10$^{-3}$ and 10$^{-7}$ A/cm$^2$ at applied voltage of 5 V.

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Electrical Properties of Pt/$LiNbO_3$/AIN/Si(100) structures (Pt/$LiNbO_3$/AIN/Si(100) 구조의 전기적 특성)

  • 정순원;정상현;인용일;김광호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.07a
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    • pp.58-61
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    • 2001
  • Metal-insulator-semiconductor (MIS) C-V properties with high dielectric AIN thin films showed no hysteresis and good interface properties. The dielectric constant of the AIN film calculated from the capacitance at the accumulation region in the capacitance-voltage(C-V) characteristics was about 8. The C-V characteristics of MFIS capacitor showed a hysteresis loop due to the ferroelectric nature of the LiNbO$_3$ thin films. Typical dielectric constant value of LiNbO$_3$ film of MFIS device was about 23. The memory window width was about 1.2V at the gate voltage of $\pm$5 V ranges. Typical gate leakage current density of the MFIS structure was the order of 10$^{-9}$ A/cm$^2$ at the range of within $\pm$500 kV/cm. The ferroelectric capacitors showed no polarization degradation up to about 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulse(peak-to-peak 8V, 50% duty cycle) in the 500kHz.

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Electrical characteristic of PZT thin film deposit by Rf-magnetron sputtering as Pb excess ratio of target (Sputtering법으로 성장한 PZT 박막의 Target의 Pb Excess에 따른 전기적 특성에 관한 연구)

  • Lee, Kyu-Il;Kang, Hyun-Il;Park, Young;Park, Ki-Yeub;Song, Joon-Tae
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2002.07b
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    • pp.570-573
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    • 2002
  • Pb(Zr0.52Ti0.48)O3 (PZT) thin films were deposited on the Pt/Ti bottom electrode by rf magnetron sputtering method from target containing 5%, 25% and 50% Pb excess for applying ferroelectric random access memory (FRAM). PZT films were deposited at $300^{\circ}C$ and then they were crystallized by rapid thermal annealing (RTA) at $700^{\circ}C$. After RTA treatment, our results showed that all PZT films indicated perovskite polycrystalline structure with preferred orientation (110) and no pyrochlore phase was observed by X-ray diffraction (XRD) and by Scanning electron microscopy (SEM). A well-fabricated PZT film of excess Pb 25% capacitor showed a leakage current density in the order of $2.63{\times}10^{-7}A/cm^2$ at 100kV/cm, a remanent polarization of $3.385{\mu}C/cm^2$ and a coercive field of 41.32 kV/cm. The results showed that Pb excess of target affects to electrical properties of PZT thin film.

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Annealing Effects of Tunneling Dielectrics Stacked $SiO_2/Si_3N_4$ Layers for Non-volatile Memory (비휘발성 메모리를 위한 $SiO_2/Si_3N_4$ 적층 구조를 갖는 터널링 절연막의 열처리 효과)

  • Kim, Min-Soo;Jung, Myung-Ho;Kim, Kwan-Su;Park, Goon-Ho;Jung, Jong-Wan;Chung, Hong-Bay;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2008.11a
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    • pp.128-129
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    • 2008
  • The annealing effects of $SiO_2/Si_3N_4$ stacked tunneling dielectrics were investigated. I-V characteristics of band gap engineered tunneling gate stacks consisted of $Si_3N_4/SiO_2/Si_3N_4$(NON), $SiO_2/Si_3N_4/SiO_2$(ONO) dielectrics were evaluated and compared with $SiO_2$ single layer using the MOS(Metal-Oxide-Semiconductor) capacitor structure. The leakage currents of engineered tunneling barriers (ONO, NON stacks) are lower than that of the conventional $SiO_2$ single layer at low electrical field. Meanwhile, the engineered tunneling barriers have larger tunneling current at high electrical field and improved electrical characteristics by annealing processes than $SiO_2$ layer.

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