Advances in nano research

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Optimized QCA SRAM cell and array in nanoscale based on multiplexer with energy and cost analysis

  • Moein Kianpour (Department of Electrical Engineering, Science and Research Branch, Islamic Azad University) ;
  • Reza Sabbaghi-Nadooshan (Department of Electrical Engineering, Central Tehran Branch, Islamic Azad University) ;
  • Majid Mohammadi (Faculty of Engineering, Shahid Bahonar University) ;
  • Behzad Ebrahimi (Department of Electrical Engineering, Science and Research Branch, Islamic Azad University)
  • Received : 2023.04.26
  • Accepted : 2023.08.22
  • Published : 2023.12.25
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Abstract

Quantum-dot cellular automata (QCA) has shown great potential in the nanoscale regime as a replacement for CMOS technology. This work presents a specific approach to static random-access memory (SRAM) cell based on 2:1 multiplexer, 4-bit SRAM array, and 32-bit SRAM array in QCA. By utilizing the proposed SRAM array, a single-layer 16×32-bit SRAM with the read/write capability is presented using an optimized signal distribution network (SDN) crossover technique. In the present study, an extremely-optimized 2:1 multiplexer is proposed, which is used to implement an extremely-optimized SRAM cell. The results of simulation show the superiority of the proposed 2:1 multiplexer and SRAM cell. This study also provides a more efficient and accurate method for calculating QCA costs. The proposed extremely-optimized SRAM cell and SRAM arrays are advantageous in terms of complexity, delay, area, and QCA cost parameters in comparison with previous designs in QCA, CMOS, and FinFET technologies. Moreover, compared to previous designs in QCA and FinFET technologies, the proposed structure saves total energy consisting of overall energy consumption, switching energy dissipation, and leakage energy dissipation. The energy and structural analyses of the proposed scheme are performed in QCAPro and QCADesigner 2.0.3 tools. According to the simulation results and comparison with previous high-quality studies based on QCA and FinFET design approaches, the proposed SRAM reduces the overall energy consumption by 25%, occupies 33% smaller area, and requires 15% fewer cells. Moreover, the QCA cost is reduced by 35% compared to outstanding designs in the literature.

Keywords

Acknowledgement

This work was supported by Shahid Rajaee Teacher Training University under grant number 4951.

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