• ETRI Journal
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• v.27 no.4
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• pp.449-452
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• 2005

The electrical characteristics of solid state devices such as the bipolar junction transistor (BJT), metal-oxide semiconductor field-effect transistor (MOSFET), and other active devices are altered by impinging photon radiation and temperature in the space environment. In this paper, the threshold voltage, the breakdown voltage, and the on-resistance for two kinds of MOSFETs (200 V and 100 V of $V_{DSS}$) are tested for ${\gamma}-irradiation$ and compared with the electrical specifications under the pre- and post-irradiation low dose rates of 4.97 and 9.55 rad/s as well as at a maximum total dose of 30 krad. In our experiment, the ${\gamma}-radiation$ facility using a low dose, available at Korea Atomic Energy Research Institute (KAERI), has been applied on two commercially available International Rectifier (IR) products, IRFP250 and IRF540.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.2
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• pp.110-119
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• 2007

A new two-dimensional analytical model for dual-material double-gate fully-depleted SOI MOSFET with Pearson-IV type Doping Distribution is presented. An investigation of electrical MOSFET parameters i.e. drain current, transconductance, channel resistance and device capacitance in DM DG FD SOI MOSFET is carried out with Pearson-IV type doping distribution as it is essential to establish proper profiles to get the optimum performance of the device. These parameters are categorically derived keeping view of potential at the center (${\phi}_c$) of the double gate SOI MOSFET as it is more sensitive than the potential at the surface (${\phi}_s$). The proposed structure is such that the work function of the gate material (both sides) near the source is higher than the one near the drain. This work demonstrates the benefits of high performance proposed structure over their single material gate counterparts. The results predicted by the model are compared with those obtained by 2D device simulator ATLAS to verify the accuracy of the proposed model.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.477-484
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• 2021

The 4kW class inverter for portable ESS designed through this study achieves lightweight and high power density by reducing the volume of passive devices (capacitors, inductors, etc.) suitable for portable use, and minimizes heat loss of the MOSFET through the low on resistance of the MOSFET. So that high efficiency can be achieved. In addition, in order to deliver high quality energy, it is designed to have a low THDV in accordance with the current KEPCO business handling guidelines, and is designed to output a sine wave with low distortion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.1-8
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• 2005

A RC parallel gate model is used to consider gate distributed effect that affects RF MOSFET performance, and extraction formula based on $Y_{11}$-parameters are used to extract model parameters directly from measured S-parameters. Better agreement between measured and modeled S-parameters in the frequency range beyond 10 GHz is achieved by using the RC parallel model than conventional Rg one, demonstrating the accuracy of the RC model and extraction technique. Using these extraction methods, gate voltage dependent curves of RC gate model parameters are newly extracted, and these parameter data will greatly contribute to developing a RF nonlinear gate model.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.195-196
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• 2005

In recent years, as the needs of MOS's a high quality is desired to get the superior electrical characteristics and reliability on MOSFET. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over MOSFET, 2'nd silicidation formation process has been proposed as a dielectric growth/annealing process. In this study the author observed process characteristics on MOS structure. In view points of the process characteristics of MOS capacitor, the oxygen & polysilicon was analyzed by SIMS analysis on l'st & 2'nd Ti process, the oxygen and Si2 contents[Count/sec] of 1.5e3 & 3.75e4 on l'st process and l.1e3 & 2.94e4 on 2'nd process, the Ti contents' of 8.2e18 & 6.5e18 on 1'st and 2'nd process. The sheet resistance[$\Omega/sq.$] was 4.5 & 4.0, the film stress[dyne/cm 2] of 1.09e10 & 1.075e10 on l'st and 2'nd process. I could achieved the superior MOS characteristics by 2'nd silicidation process.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1057-1060
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• 2003

This paper is about the optimized fabricated parameter in the EDMOSFET(Extended drain MOSFET) with a various temperature. As we know, the two important factors of EDMOSFET parameters are breakdown voltage and on Resistance. So, we have aims of the power EDMOSFET design to have high breakdown voltage and low on resistance. Thus in this paper, we will show the figure of merit in LDMOS (BV/Ron) in accordance with increase in temperature(300K-500K, step:50K), and measure electronic characteristics of power EDMOSFET. As a result, the important factors in design of EDMOS are temperature and Lg.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.4
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• Journal of IKEEE
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• v.14 no.3
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• pp.250-255
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• 2010

The interleaved power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device is proposed in this paper. The buck-boost converter used to provide the high output voltage and low output voltage for portable applications. Also we used the PWM(Pulse Width Modulation) control method for high power efficiency at high current level. DTMOS with low on-resistance is designed to decrease conduction loss. The interleaved PMIC to reduce output ripple. And step-down DC-DC converter in stand-by mode below 1mA is designed with LDO in order to achive high efficiency.

• International journal of advanced smart convergence
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• v.9 no.2
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• pp.105-113
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• 2020

In this paper, we proposed a soft switched synchronous boost converter, which can perform discharging the battery, is proposed. The proposed converter has low switching loss even at high frequency operation due to its soft switching characteristics. The converter operates in synchronous mode to minimize conduction loss because of changing the rectified diode to MOSFET with a low on resistance. In this reason, the efficiency of the converter can be greatly improved in high frequency. In this paper, the battery discharger with a switching frequency of 100 kHz, has been designed. The designed converter also simulated to prove the converter's characteristics of synchronous operation as well as soft switching operation. The simulation shows that the proposed converter always meets the soft switching conditions of turning on and off switching in the zero voltage and zero current states. Therefore, simulation results have confirmed that the proposed battery discharge had soft switching characteristics. The simulation results have confirmed that the proposed battery discharger had soft switching and synchronous operation characteristics.

• Journal of IKEEE
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• v.24 no.2
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• pp.619-625
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• 2020

In this paper, we propose a TS-DMOSFET(Trench Shielded DMOSFET) structure in which P+ shielding region is formed in a deeper region than C-DMOSFET(Conventional DMOSFET) and S-DMOSFET(Shielded DMOSFET). Using TCAD simulation to compare the static characteristics of TS-DMOSFET with C- and S-DMOSFET. As for the structure proposed, the doping is followed by the source trench process. Despite the fact that it is a SiC material, this allows it to form a P+ shielding region in a deep area. Followed by completely suppressing the reach-through effect. As a result, when the breakdown voltage of the three structures is 3.3kV, the Ron of TS-DMOSFET is 9.7mΩ㎠. Thus, it is 68% and 54% smaller than the Ron of C-DMOSFET and S-DMOSFET respectively.