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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Low Resistance 3.3kV 4H-SiC Trench Shielded DMOSFET

Trench Shield 구조를 갖는 3.3kV급 저저항 4H-SiC DMOSFET

  • Cha, Kyu-hyun (Dept. of Electronics Engineering, Sogang University) ;
  • Kim, Kwang-su (Dept. of Electronics Engineering, Sogang University)
  • Received : 2020.06.16
  • Accepted : 2020.06.24
  • Published : 2020.06.30
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Abstract

In this paper, we propose a TS-DMOSFET(Trench Shielded DMOSFET) structure in which P+ shielding region is formed in a deeper region than C-DMOSFET(Conventional DMOSFET) and S-DMOSFET(Shielded DMOSFET). Using TCAD simulation to compare the static characteristics of TS-DMOSFET with C- and S-DMOSFET. As for the structure proposed, the doping is followed by the source trench process. Despite the fact that it is a SiC material, this allows it to form a P+ shielding region in a deep area. Followed by completely suppressing the reach-through effect. As a result, when the breakdown voltage of the three structures is 3.3kV, the Ron of TS-DMOSFET is 9.7mΩ㎠. Thus, it is 68% and 54% smaller than the Ron of C-DMOSFET and S-DMOSFET respectively.

본 논문에서는 Trench를 이용하여 기존 C-DMOSFET(Conventional DMOSFET)과 S-DMOSFET(Shielded DMOSFET) 구조보다 더 깊은 영역에 P+ shielding을 형성한 TS-DMOSFET(Trench Shielded DMOSFET) 구조를 제안하였으며 TCAD 시뮬레이션을 통해 C- 및 S-DMOSFET 구조와 전기적 특성을 비교하였다. 제안한 구조는 Source에 Trench를 형성한 후 도핑을 진행하므로 SiC 물질 특성과 관계없이 깊은 영역에 P+ shielding을 형성할 수 있다. 이로 인해 P-base에 인가되는 전압이 감소하여 리치스루 효과가 완화되었다. 그 결과 세 구조 모두 3.3kV의 항복 전압을 가질 때 제안한 구조의 온저항은 9.7mΩ㎠으로 C-DMOSFET과 S-DMOSFET의 온저항인 30.5mΩ㎠, 19.3mΩ㎠ 대비 각각 68%, 54% 개선된 온저항을 갖는다.

Keywords

References

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