• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.1
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• pp.40-47
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• 2003

A low-cost current-sensing scheme for the motor drives with MOSFET is described. Many motor drives usually employ the common current sensors to measure current for the purpose of control or protection. These current sensors, however, significantly burden the power circuit with the size and cost. The proposed current-sensing scheme utilizes information concerning MOSFET's On-voltage and On-resistance. An analogue circuit detecting On-voltage can overcome the above disadvantages because the circuit is small and is made at a low cost, and the fuzzy inference for On-resistance is also simply designed based on MOSFET's characteristics. The validity of this scheme will be experimentally verified by adopting the current control of a battery car.

• Proceedings of the KIEE Conference
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• 1996.11a
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• pp.457-461
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• 1996

An optimum design methodology for the power MOSFET's with a predetermined mask is proposed and verified by comparing with the results of MEDICI simulation and the data of commercially available devices. Optimization is completed by determining a doping concentration and a thickness of the epitaxial layer which satisfy a specific voltage and current rating requirements as well as a minimum on-resistance for the mask set. The commercial HEX-1 mask set with a die area of $40.4{\times}10^{-3}\;cm^2$ and a T0-220 package has the on-resistance of $1.5{\Omega}$ at 200 V/2.5 A rating while the M-1 mask from this study exhibits $0.6{\Omega}$ on-resistance at 200 V/6 A. The 60 % reduction in the on-resistance and 58 % enhancement in the current rating have been obtained by the proposed method.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.5 no.1
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• pp.13-15
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• 2004

The current driven in an MOSFET is limited by the intrinsic channel resistance. All the other parasitic elements in a device structure play a significant role and degrade the device performance. These other resistances need to be less than 15％ of the channel resistance. To achieve the requirements, we should investigate the methodology of separation and quantification of those resistances. In this paper, we developed the extraction method of resistances using calibrated TCAD simulation. The resistance of the extension region is also partially determined by the formation of a surface accumulation region that forms under the gate in the tail region of the extension profile. This resistance is strongly affected by the abruptness of the extension profile because the steeper the profile is, the shorter this accumulation region will be.

• Journal of IKEEE
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• v.24 no.2
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• pp.592-597
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• 2020

Since SiC has 10 times higher breakdown field and 3 times higher energy gap than Si, it is possible to manufacture an excellent power MOSFET with a high breakdown voltage. However, since it has a high on-resistance due to low mobility, a Trench MOSFET has been proposed to lower it, but at the same time, it has a problem that BV decreases. The purpose of this paper is to design a 1200V trench MOSFET, and to solve this, split Epi depth, Trench depth, and Trench depth to Epi depth, which are important variables for BV and Ron, to achieve maximum electric field, BV, Ron's reliability characteristics were compared and analyzed. As the epi depth increased, the trench depth decreased, and the epi depth decreased at the trench depth, the maximum electric field decrease, BV increase, and Ron increase were confirmed. All results were simulated by sentaurus TCAD.

• Journal of the Institute of Convergence Signal Processing
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• v.11 no.2
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• pp.163-168
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• 2010

This paper presents the practical implementation of an over-temperature protection system for power semiconductor devices. In the proposed system, temperature variation is provided with just using $R_{ds(on)}$ characteristics of power MOSFET, while extra device such as a temperature sensor or an over-temperature detection transistor is needed to monitor the temperature in the conventional method. The proposed protection technique is experimentally tested on IRF840 power MOSFET. The PIC microcontroller PIC16F877A is used for the implementation of the proposed protection algorithm. The built-in 10-bit A/D converter is utilized for detecting voltage variance between a drain and a source of IRF840. The induced temperature-resistance relationship based on the measured drain-source voltage, supplies a gate signal to the power MOSFET. If detected temperature's voltage exceeds any a protection temperature's voltage, the microcontroller removes the trigger signal from the power MOSFET. These test results showed satisfactory performances of the proposed protection system in term of accuracy within 1.5%.

• Journal of IKEEE
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• v.20 no.2
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• pp.163-166
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• 2016

It is important to operate the driving circuit under the optimal condition through precisely sensing the power consumption causing the temperature made mainly by the MOSFET (metal-oxide semiconductor field-effect transistor) when a BLDC (Brushless Direct Current) motor operates. In this letter, a Super-junction (SJ) power TMOSFET (trench metal-oxide semiconductor field-effect transistor) with an ultra-low specific on-resistance of $0.96m{\Omega}{\cdot}cm^2$ under the same break down voltage of 100 V is designed by using of the SILVACO TCAD 2D device simulator, Atlas, while the specific on-resistance of the traditional power MOSFET has tens of $m{\Omega}{\cdot}cm^2$, which makes the higher power consumption. The SPICE simulation for measuring the power distribution of 25 cells for a chip is carried out, in which a unit cell is a SJ Power TMOSFET with resistor arrays. In addition, the power consumption for each unit cell of SJ Power TMOSFET, considering the number, pattern and position of bonding, is computed and the power distribution for an ANSYS model is obtained, and the SJ Power TMOSFET is designed to make the power of the chip distributed uniformly to guarantee it's reliability.

• Journal of IKEEE
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• v.26 no.4
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• pp.728-735
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• 2022

In this work, we investigated a high-voltage (~4.5 kV) 4H-SiC power DMOSFET with modifications of current spreading layer (CSL), which was introduced below the p-well region for low on-resistance. These include the following: 1) a thickness of CSL (T_CSL) from 0 um to 0.9 um; 2) a doping concentration of CSL (N_CSL) from 1×10¹⁶ cm^-3 to 5×10¹⁶ cm^-3. The design is optimized using TCAD 2D-simulation, and we found that CSL helps to reduce specific on-resistance but also breakdown voltage. The resulting structures exhibit a specific on-resistance (R_on,sp) of 59.61 mΩ·cm², a breakdown voltage (V_B) of 5 kV, and a Baliga's Figure of Merit (BFOM) of 0.43 GW/cm².

• Journal of IKEEE
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• v.20 no.3
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• pp.220-225
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• 2016

In this paer, low on-resistance and high-power trench gate MOSFET (Metal-Oxide-Silicon Field Effect Transistor) incorporating current sensing FET (Field Effect Transistor) is proposed and evaluated. The trench gate power MOSFET was fabricated with $0.6{\mu}m$ trench width and $3.0{\mu}m$ cell pitch. Compared with the main switching MOSFET, the on-chip current sensing FET has the same device structure and geometry. In order to improve cell density and device reliability, self-aligned trench etching and hydrogen annealing techniques were performed. Moreover, maintaining low threshold voltage and simultaneously improving gate oxide relialility, the stacked gate oxide structure combining thermal and CVD (chemical vapor deposition) oxides was adopted. The on-resistance and breakdown voltage of the high density trench gate device were evaluated $24m{\Omega}$ and 100 V, respectively. The measured current sensing ratio and it's variation depending on the gate voltage were approximately 70:1 and less than 5.6 %.

• Journal of IKEEE
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• v.28 no.1
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• pp.46-52
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• 2024

In this study, we investigated the electrical characteristics of SiC MOSFETs by depositing Si and oxidizing it to form the gate oxide layer. A thin Si layer was deposited approximately 20 nm thick on top of the SiC epi layer, followed by oxidation to form a gate oxide layer of around 55 nm. We compared devices with gate oxide layers produced by oxidizing SiC in terms of interface trap density, on-resistance, and field-effect mobility. The fabricated devices achieved improved interface trap density (~8.18 × 10¹¹ eV^-1cm^-2), field-effect mobility (27.7 cm²/V·s), and on-resistance (12.9 mΩ·cm²).

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.520-524
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• 2001

Recently, the demand of large capacity SMPS for industrial area is increasing. Full-bridge dc-dc converter with IGBT is most widely used for large capacity SMPS because IGBT has a low-conduction loss and large current capacity, But most large capacity Full-bridge do-dc converter using IGBT has low operating frequency because of switching loss at IGBT especially at turn-off by current tail and it's cause of relatively big converter size. MOSFET has low switching losses has been widely used for high frequency SMPS but it has a problem to apply to large capacity SMPS because it has large conduction resistance causing large on-time losses. In this paper, for reduction losses at switching device, MOSFET is applied at parallel with IGBT in full-bridge dc/dc converter.