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Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
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Electrical Characteristics of SiC MOSFET Utilizing Gate Oxide Formed by Si Deposition

Si 증착 이후 형성된 게이트 산화막을 이용한 SiC MOSFET의 전기적 특성

  • Young-Hun Cho (Dept. of Electronic materials Engineering, Kwangwoon University) ;
  • Ye-Hwan Kang (Dept. of Electronic materials Engineering, Kwangwoon University) ;
  • Chang-Jun Park (Dept. of Electronic materials Engineering, Kwangwoon University) ;
  • Ji-Hyun Kim (Dept. of Electronic materials Engineering, Kwangwoon University) ;
  • Geon-Hee Lee (Dept. of Electronic materials Engineering, Kwangwoon University) ;
  • Sang-Mo Koo (Dept. of Electronic materials Engineering, Kwangwoon University)
  • Received : 2024.03.20
  • Accepted : 2024.03.25
  • Published : 2024.03.31
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Abstract

In this study, we investigated the electrical characteristics of SiC MOSFETs by depositing Si and oxidizing it to form the gate oxide layer. A thin Si layer was deposited approximately 20 nm thick on top of the SiC epi layer, followed by oxidation to form a gate oxide layer of around 55 nm. We compared devices with gate oxide layers produced by oxidizing SiC in terms of interface trap density, on-resistance, and field-effect mobility. The fabricated devices achieved improved interface trap density (~8.18 × 1011 eV-1cm-2), field-effect mobility (27.7 cm2/V·s), and on-resistance (12.9 mΩ·cm2).

이번 연구에서 우리는 게이트 산화막을 형성하기 위해 Si을 증착한 후 산화시킨 SiC MOSFET의 전기적 특성을 연구했다. 고품질의 Si/SiO2 계면을 제작하기 위해 얇은 Si 층을 SiC epi 층 위에 약 20 nm을 증착한 후 산화하여 게이트 산화막을 약 55 nm로 형성했다. SiC를 산화하여 게이트 산화막을 제작한 소자와 계면 트랩 밀도, 온저항, 전계-효과 이동도의 측면에서 비교했다. 위 소자는 향상된 계면 트랩 밀도 (~8.18 × 1011 eV-1cm-2), 전계-효과 이동도 (27.7 cm2/V·s), 온저항 (12.9 mΩ·cm2)을 달성하였다.

Keywords

Acknowledgement

This work was supported by the Fostering Global Talents for Innovative Growth Program through KIAT (P0012451 and P0017308) of the MOTIE and Research Grant from Kwangwoon University in 2024.

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