• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.1033-1034
• /
• 2005

High resolution 2.1” QVGA LTPS LCD (190ppi) having high aperture ratio of 65% could be successfully developed using state-of-the-art SLS technology and active/gate storage structure. Cost effective P-MOS 6-Mask structure was used. Full gate and transmission gate circuits are integrated in the panel. The high aperture ratio was obtained by using active/gate capacitance structure, which can reduce storage capacitance area. The aperture ratio was increased to 65% from 49% of conventional gate/data capacitance structure. The brightness was increased from 180cd to 270cd without any degradation of optical properties such as contrast ratio, flicker or crosstalk.

• Journal of the Korean Chemical Society
• /
• v.50 no.4
• /
• pp.281-290
• /
• 2006

The electronic structure and properties of the 1H-indene and mono-sila-1H-indene series have been investigated using basis set of 6-31G(d, p) and hybrid density functional theory. Basic measures of aromatic character derived from structure, molecular orbitals, a variety of magnetic criteria (magnetic isotropic and anisotropic susceptibilities) are considered. Energetic criteria suggest that In(Si7) enjoy conspicuous stabilization. However, by magnetic susceptibility isotropic this system are among the least aromatic of the family: Within their isomer series, In(Si4) is the most aromatic using this criteria. Natural bond orbital (NBO) analysis method was performed for the investigation of the relative stability and the nature of the 8-9 bonds in 1H-indene and mono-sila-1H-indene compounds. The results explained that how the p character of natural atomic hybrid orbital on X8 and X9 (central bond) is increased by the substitution of the C8 and C9 by Si. Actually, the results suggested that in these compounds, the X8-X9 bond lengths are closely controlled by the p character of these hybrid orbitals and also by the nature of C-Si bonds. The magnitude of the molecular stabilization energy associated to delocalization from X8-X9 and to * X8-X9 bond orbital were also quantitatively determined. Molecular orbital (MO) analysis further reveal that all structure has three delocalized MOs and two delocalized MOs and therefore exhibit the aromaticity.

• Transactions on Electrical and Electronic Materials
• /
• v.5 no.5
• /
• pp.169-172
• /
• 2004

Deep sub-micron device required to get the superior ultra thin gate oxide characteristics. In this research, I will recommend a novel shallow trench isolation structure(STI) for thin gate oxide and a $N_2$O gate oxide 30 $\AA$ by NO ambient process. The local oxidation of silicon(LOCOS) isolation has been replaced by the shallow trench isolation which has less encroachment into the active device area. Also for $N_2$O gate oxide 30 $\AA$, ultra thin gate oxide 30 $\AA$ was formed by using the $N_2$O gate oxide formation method on STI structure and LOCOS structure. For the metal electrode and junction, TiSi$_2$ process was performed by RTP annealing at 850 $^{\circ}C$ for 29 sec. In the viewpoints of the physical characteristics of MOS capacitor, STI structure was confirmed by SEM. STI structure was expected to minimize the oxide loss at the channel edge. Also, STI structure is considered to decrease the threshold voltage, result in a lower Ti/TiN resistance( Ω /cont.) and higher capacitance-gate voltage(C- V) that made the STI structure more effective. In terms of the TDDB(sec) characteristics, the STI structure showed the stable value of 25 % ～ 90 % more than 55 sec. In brief, analysis of the ultra thin gate oxide 30 $\AA$ proved that STI isolation structure and salicidation process presented in this study. I could achieve improved electrical characteristics and reliability for deep submicron devices with 30 $\AA$ $N_2$O gate oxide.

• Journal of Internet of Things and Convergence
• /
• v.6 no.1
• /
• pp.97-102
• /
• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• Journal of the Korean Vacuum Society
• /
• v.5 no.4
• /
• pp.333-340
• /
• 1996

The properties of TiN as a barrier against Cu diffusion ere studied by sheet resistance measurement, X-ray diffraction, scanning electron microscopy, Auger electron spectroscopy, and capacitance-voltage(C-V) measurement. The sensitivities of the various methods were compared. Specimens with Cu/TiN/Ti/SiO2/Si structure were prepared by various deposition techniques and annealed at various temperatures ranging from $500^{\circ}C$ to $800^{\circ}C$ in 10%H2/90%Ar ambient for hours. As the effectiveness of the barrier property of TiN against Cu diffusion was vanished, the irregular-shaped sports were observed and outdiffused Si were detected on the surface of the Cu thin film. The C-V characteristics of the MOS capacitors varied drastically with annealing temperatures. In C-V measurement, the inversion capacitance decreased at annealing temperature range from $500^{\circ}C$ to $700^{\circ}C$ and increased remarkably at $800^{\circ}C$. These variations may be due to the Cu diffusion through TiN into $SiO_2$ and Si.

• Korean Journal of Materials Research
• /
• v.5 no.1
• /
• pp.3-11
• /
• 1995

$(TiO_{2})$ thin films were deposited on p-Si(100) substrate by APMOCVD using titanium isopropoxide as a source material. The deposition mechanism was well explained by the simple boundary layer theory and the apparent activation energy of the chemical reaction controlled process was 18.2kcal /mol. The asdeposited films were polycrystalline anatase phase and were transformed into rutile phase after postannealing. The postannealing time and the film thikness as well as the postannealing temperature also affected the phase transition. The C-V plot exhibited typical charateristics of MOS diode, from which the dielectric constant of about 80 was obtained. The capacitance of the annealed film was decreased but those of the Nb or Sr doped films were not changed. I-V characteristics revealed that the conduction mechanism was hopping conduction. The postannealing and the doping of Nb or Sr cause to decrease the leakage current and to increase the breakdown voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.4
• /
• pp.32-38
• /
• 2011

This paper describes implementation of the 5.0GHz RF frequency synthesizer with 0.18${\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get excellent performance of high speed and wide tuning range, N-P MOS core structure and 12 step cap banks have been used in design of the VCO. The chip area including pads for testing is $1.1{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.0{\times}0.4mm^2$. Through analysing of the fabricated frequency synthesizer, we can see that it has wide operation range and excellent frequency characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.5
• /
• pp.49-54
• /
• 2009

This paper describes implementation of the 1.9GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma }-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.2{\times}0.7mm^2$, and the chip area only core for IP in SoC is $1.1{\times}0.4mm^2$. The test results show that there is no special spurs except -63.06dB of the 6MHz reference spurs in the PLL circuitry. There is good phase noise performance like -116.17dBc/Hz in 1MHz offset frequency.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.45 no.6
• /
• pp.87-93
• /
• 2008

This paper describes implementation of the 5.0GHz RF frequency synthesizer with $0.18{\mu}m$ silicon CMOS technology being used as an application of the IEEE802.15.4 USN sensor node transceiver modules. To get good performance of speed and noise, design of the each module like VCO, prescaler, 1/N divider, fractional divider with ${\Sigma}-{\Delta}$ modulator, and common circuits of the PLL has been optimized. Especially to get good performance of speed, power consumption, and wide tuning range, N-P MOS core structure has been used in design of the VCO. The chip area including pads for testing is $1.1*0.7mm^2$, and the chip area only core for IP in SoC is $1.0*0.4mm^2$. Through comparing and analysing of the designed two kind of the frequency synthesizer, we can conclude that if we improve a litter characteristics there is no problem to use their as IPs.

• The Journal of the Acoustical Society of Korea
• /
• v.19 no.4
• /
• pp.37-44
• /
• 2000

In this paper, we described the real-time implementation effort of MPEG-4 audio HVXC (Harmonic Vector eXcitation Coding) algorithm for very low bitrates, which has target applications from mobile communications to Internet telephony, on current high performance floating point TMS320C6701 DSP. We adopted a hardware structure for real-time operation. In order for software optimization, we used C- and assembly-language level optimizations for time-critical functional codes. Utilizing the internal program memory of the DSP as the program cache, the internal data memory overlap technique and DMA functionality, we could get a goal of realtime operation of HVXC codec both at 2 kbit/s and at 4 kbit/s. For an encoder at 2 kbit/s, the optimization ratio to original code is about 96 %. Finally, we got the subjective quality of MOS 2.45 at 2 kbit/s from an informal quality test.