• Title/Summary/Keyword: Low input

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Family of Dual-Input Dual-Buck Inverters Based on Dual-Input Switching Cells

  • Yang, Fan;Ge, Hongjuan;Yang, Jingfan;Dang, Runyun;Wu, Hongfei
    • Journal of Power Electronics
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    • v.18 no.4
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    • pp.1015-1026
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    • 2018
  • A family of dual-DC-input (DI) dual-buck inverters (DBIs) is proposed by employing a DI switching cell as the input of traditional DBIs. Three power ports, i.e. a low voltage DC input port, a high voltage DC input port and an AC output port, are provided by the proposed DI-DBIs. A low voltage DC source, whose voltage is lower than the peak amplitude of the AC side voltage, can be directly connected to the DI-DBI. This supplies power to the AC side in single-stage power conversion. When compared with traditional DBI-based two-stage DC/AC power systems, the conversion stages are reduced, and the power rating and power losses of the front-end Boost converter of the DI-DBI are reduced. In addition, five voltage-levels are generated with the help of the two DC input ports, which is a benefit in terms of reducing the voltage stresses and switching losses of switches. The topology derivation method, operation principles, modulation strategy and characteristics of the proposed inverter are analyzed in-depth. Experimental results are provided to verify the effectiveness and feasibility of the proposed DI-DBIs.

A 3.3V/5V Low Power TTL-to-CMOS Input Buffer Controlled by Internal Activation Clock Pulse (활성 클럭펄스로 제어되는 3.3V/5V 저전력 TTL-to-CMOS 입력 버퍼)

  • Bae, Hyo-Kwan;Ryu, Beom-Seon;Cho, Tae-Won
    • Journal of IKEEE
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    • v.5 no.1 s.8
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    • pp.52-58
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    • 2001
  • This paper describes a TTL-to-CMOS input buffer of an SRAM which dissipates a small operating power dissipation. The input buffer utilizes a transistor structure with latch circuit controlled by a internal activation clock pulse. During the low state of that pulse, input buffer is disabled to eliminate dc current. Otherwise, the input buffer operates normally. Simulation results showed that the power-delay product of the purposed input buffer is reduced by 33.7% per one input.

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Unbalance Control Strategy of Boost Type Three-Phase to Single-Phase Matrix Converters Based on Lyapunov Function

  • Xu, Yu-xiang;Ge, Hong-juan;Guo, Hai
    • Journal of Power Electronics
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    • v.19 no.1
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    • pp.89-98
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    • 2019
  • This paper analyzes the input side performance of a conventional three-phase to single-phase matrix converter (3-1MC). It also presents the input-side waveform quality under this topology. The suppression of low-frequency input current harmonics is studied using the 3-1MC plus capacitance compensation unit. The constraint between the modulation function of the output and compensation sides is analyzed, and the relations among the voltage utilization ratio and the output compensation capacitance, filter capacitors and other system parameters are deduced. For a 3-1MC without large-capacity energy storage, the system performance is susceptible to input voltage imbalance. This paper decouples the inner current of the 3-1MC using a Lyapunov function in the input positive and negative sequence bi-coordinate axes. Meanwhile, the outer loop adopts a voltage-weighted synthesis of the output and compensation sides as a cascade of control objects. Experiments show that this strategy suppresses the low-frequency input current harmonics caused by input voltage imbalance, and ensures that the system maintains good static and dynamic performances under input-unbalanced conditions. At the same time, the parameter selection and debugging methods are simple.

Four Quadrant CMOS Current Differentiated Circuit

  • Parnklang, Jirawath;Manasaprom, Ampaul;Ukritnukul, Anek
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.948-950
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    • 2003
  • In this literature, the CMOS current mode fout quadrant differentiator circuit is proposed. The implementation is base on an appropriate input stage that converts the input current into a compressed voltage at the input capacitor ($C_{gs}$) of the CMOS driver circuit. This input voltage use as the control output current which flow to the output node by passing through a MOS active load and use it as the feedback voltage to the input node. Simulation results with level 49 CMOS model of MOSIS are given to demonstrate the correct operation of the proposed configuration. But the gain of the circuit is too low so the output differentiate current also low. The proposed differentiator is expected to find several applications in analog signal processing system.

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A Novel Two-Switch Active Clamp Forward Converter for High Input Voltage Applications

  • Kim, Jae-Kuk;Oh, Won-Sik;Moon, Gun-Woo
    • Proceedings of the KIPE Conference
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    • 2008.06a
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    • pp.520-522
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    • 2008
  • A novel two-switch active clamp forward converter suitable for high input voltage applications is proposed. The main advantage of the proposed converter, compared to the conventional active forward converters, is that circuit complexity is reduced and the voltage stress of the main switches is effectively clamped to either the input voltage or the clamping capacitor voltage by two clamping diodes without limiting the maximum duty ratio. Also, the clamping circuit does not include additional active switches, so a low cost can be achieved without degrading the efficiency. Therefore, the proposed converter can feature high efficiency and low cost for high input voltage applications. The operational principles, features, and design considerations of the proposed converter are presented in this paper. The validity of this study is confirmed by the experimental results from a prototype with 200W, 375V input, and 12V output.

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Dynamic Analysis and Driving Input Shaping of Inchworm (이송자벌레의 동적 해석 및 구동 입력신호 설계)

  • Kim, In-Soo;Kim, Yeung-Shik
    • Transactions of the Korean Society for Noise and Vibration Engineering
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    • v.18 no.7
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    • pp.756-763
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    • 2008
  • This paper presents an inchworm with three piezoelectric actuators. The dynamic stiffness of the inchworm is generally low compared to its driving condition, so mechanical vibration may degenerate the motion accuracy of the inchworm. The dynamic model of inchworm is identified by curve fitting technique based on the experimental frequency response function. For the precision motion control and low residual vibration of inchworm, driving input signal is designed by using cycloid step input and LQG control technique. Experimental result shows that proposed input shaping method is applicable effectively to the inchworm.

Experiment of a 3D Motion Input Device (3차원 운동 입력장치 구현)

  • Lee, Woo-Won;Choi, Myoung-Hwan
    • Journal of Industrial Technology
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    • v.19
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    • pp.173-178
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    • 1999
  • In many areas of technology there are machines and systems controllable in up to six degrees of freedom. Helicopters and underwater vehicles, industrial robots are among the first representatives of this category. They need six degrees of freedom in order to move and orient within their workspace. An even broader and more explosively growing area is 3D computer graphics and virtual environment. In this work, functions of 3D input device are described and two types of commercial 3D input device are presented. Then, a preliminary experiment of a low cost 6 axis force/moment sensor is presented that can also be sued as a 3D input device. A low cost force/moment sensor and its application in robot teaching experiment is described. It computes the direction of 3 components of the force and 3 components of the moment applied by human holding the sensor by hand. The concept is shown by an experiment where the tool position and orientation of a robot in 3 dimensional space is controlled by the proposed sensor.

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LVDS I/O Cells with Rail-to-Rail Input Receiver

  • Lim, Byong-Chan;Lee, Sung-Ryong;Kwon, Oh-Kyong
    • 한국정보디스플레이학회:학술대회논문집
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    • 2002.08a
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    • pp.567-570
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    • 2002
  • The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.

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SVPWM controlled the Three-phase AC to DC Boost Converter for High Power Factor (SVPWM 방식의 3상 고역율 AC-DC Boost 컨버터)

  • Na, Jae-Hyeong;Lee, Jung-Hyo;Kim, Kyung-Min;Lee, Su-Won;Won, Chung-Yuen
    • Proceedings of the Korean Institute of IIIuminating and Electrical Installation Engineers Conference
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    • 2008.10a
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    • pp.327-331
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    • 2008
  • The problems of power factor and harmonics are occurred in converter system which used to SCRs and diodes as power semiconductor devices IGBT was solved that problem, maintain the input line current with sinusoidal wave current of input power source voltage. In this paper, three phase AC to DC boost converter that operates with unity power factor and sinusoidal input currents is presented. The current control of the converter is based on the space vector PWM strategy with fixed switching frequency and the input current tracks the reference current within one sampling time interval. Space vector PWM strategy for current control was materialized as a digital control method. By using this control strategy low ripples in the output voltage, low harmonics in the input current and fast dynamic responses are achieved with a small capacitance in the dc link.

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Standby Power Reduction Technique due to the Minimization of voltage difference between input and output in AC 60Hz (대기전력 최소화를 위한 교류전압 입력에 따른 저전압 구동회로 설계)

  • Seo, Kil-Soo;Kim, Ki-Hyun;Kim, Hyung-Woo;Lee, Kyung-Ho;Kim, Jong-Hyun
    • Proceedings of the KIEE Conference
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    • 2015.07a
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    • pp.1018-1019
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    • 2015
  • Recently, standby power reduction techniques of AC/DC adaptor were developed, consuming power almost arrived to 300mW level. The standby power losses are composed of the input filter loss 11.8mW, the control IC for AC/DC adaptor 18mW, the switching loss 9.53mW and the feedback loss 123mW. And there are the standby power reduction techniques. In this paper, in order to reduce the standby power of SMPS more, the loss due to a voltage difference between input and output is reduced by the control circuit which is composed of the low voltage driving circuit and voltage regulator. The low voltage driving circuit operates on the low voltage of input and off the high voltage. The low voltage driving IC was produced by the $1.0{\mu}m$, high voltage DMOS process.

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