Standby Power Reduction Technique due to the Minimization of voltage difference between input and output in AC 60Hz

대기전력 최소화를 위한 교류전압 입력에 따른 저전압 구동회로 설계

  • Seo, Kil-Soo (Power Semiconductor Research Center, Korea Electrotechnology Research Institute) ;
  • Kim, Ki-Hyun (Power Semiconductor Research Center, Korea Electrotechnology Research Institute) ;
  • Kim, Hyung-Woo (Power Semiconductor Research Center, Korea Electrotechnology Research Institute) ;
  • Lee, Kyung-Ho (Power Semiconductor Research Center, Korea Electrotechnology Research Institute) ;
  • Kim, Jong-Hyun (Power Semiconductor Research Center, Korea Electrotechnology Research Institute)
  • 서길수 (전력반도체연구센터 한국전기연구원) ;
  • 김기현 (전력반도체연구센터 한국전기연구원) ;
  • 김형우 (전력반도체연구센터 한국전기연구원) ;
  • 이경호 (전력반도체연구센터 한국전기연구원) ;
  • 김종현 (전력반도체연구센터 한국전기연구원)
  • Published : 2015.07.15

Abstract

Recently, standby power reduction techniques of AC/DC adaptor were developed, consuming power almost arrived to 300mW level. The standby power losses are composed of the input filter loss 11.8mW, the control IC for AC/DC adaptor 18mW, the switching loss 9.53mW and the feedback loss 123mW. And there are the standby power reduction techniques. In this paper, in order to reduce the standby power of SMPS more, the loss due to a voltage difference between input and output is reduced by the control circuit which is composed of the low voltage driving circuit and voltage regulator. The low voltage driving circuit operates on the low voltage of input and off the high voltage. The low voltage driving IC was produced by the $1.0{\mu}m$, high voltage DMOS process.

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