• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2000년도 학술대회논문집
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• pp.155-159
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• 2000

This paper describes the self healing characteristics of metalized polypropylene film(MPPF) under ac condition. PDs were generally observed at relatively low voltage, and the PDIVs were differently varied depending on the number of pre-self healing due to void defects. Several pre-self healing events took place at lower voltage than the critical breakdown voltage of PPF. Self healing mainly occurred at pin tips, wrinkle sides, and cross points of wrinkles. The applied voltage at self healing was increased with PPF thickness. The burn out area at self healing was also increased with the applied voltage and PPF thickness. The peak currents in a grounding conductor at self healing was also increased with the applied voltage.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.948-950
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• 2003

In this literature, the CMOS current mode fout quadrant differentiator circuit is proposed. The implementation is base on an appropriate input stage that converts the input current into a compressed voltage at the input capacitor ($C_{gs}$) of the CMOS driver circuit. This input voltage use as the control output current which flow to the output node by passing through a MOS active load and use it as the feedback voltage to the input node. Simulation results with level 49 CMOS model of MOSIS are given to demonstrate the correct operation of the proposed configuration. But the gain of the circuit is too low so the output differentiate current also low. The proposed differentiator is expected to find several applications in analog signal processing system.

• 전기학회논문지P
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• 제54권4호
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• pp.179-184
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• 2005

This paper examines the application of high voltage static var compensator(SVC) with cascade multilevel inverter which employs H-bridge inverter(HBI). A new switching scheme is developed for the SVC system. To improve the unbalanced problem of the DC capacitor voltages, the rotated switching scheme of fundamental frequency is newly used. The optimized fundamental switching pattern with low switching frequency is adapted to be suitable for high application. The selective harmonic elimination method(SHEM) allows to keep the total harmonic distortion(THD) low in the output voltage of multilevel inverter. The SVC system is modeled using the d-q transform which calculates the instantaneous reactive power. This model is used to design a controller and analyze the SVC system. Simulated and experimental results are also presented and discussed to validate the proposed schemes.

• 전기학회논문지P
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• 제51권1호
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• pp.10-17
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• 2002

Due to the development of information communication field, the interest of the SMPS(Switched Mode Power Supply) is increased. The size and weight of SMPS are decided by inductor, capacitor and transformer. Thus, the low loss converter which is operated in high speed switching is required. The resonant FB DC-DC converter is able to operate in high speed switching and apply to high power field because the switching loss is low. In this thesis, it is proposed to control strategy for constant output power of resonant FB DC-DC converter in variable input voltage. The proposed control system is a digital I-PD type control and apply to phase-shift resonant type controller. The output voltage tracks reference without steady state error in variable input voltage. The validity of proposed control strategy is verified from results of simulation and experiment.

• 대한전자공학회논문지
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• 제19권6호
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• pp.41-51
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• 1982

본 논문에서는 V[S(voltage inverter switch)를 사용한 SCF(switched capacitor filler)에 있어서 VIS의 비이상적인 동작이 여파기 특성에 미치는 영향을 여파기를 구성하는 각 소자들의 변화로써 분석하는 방법을 제시하였다. 또 위의 결과를 VIS가 없는 SCF의 경우에 응용함으로써 대부분의 SC(switched cavacito.) 회로를 쌍일차(bilinear) 변환된 영역에서 그 등가각로를 쉽게 구할 수 있어 SCF의 분석이 용이하고, 높은동작 주파수를 갖는 SCF를 적은 수의 능동 소자로 구현할 수 있는 방법에 대해 기술하였다. 그리고 저역 통과 여파기와 대역 저지 여파기를 실험하여 그 결과가 이론치와 잘 일치함을 보였다.

• 전력전자학회논문지
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• 제17권2호
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• pp.182-189
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• 2012

In this paper, the input current and output voltage ripple of the soft switching interleaved boost converter was analyzed. Ripples of input current and output voltage with an interleaved method is analysed and as a result, the facts that it has lower ripple current than conventional interleaved method is verified. it means that a capacity of a main inductor can be reduced. Besides, a low capacitance of capacitor which means high lifetime and confidence can be used because of reducing ripples of output voltage. In order to verify the validity of the proposed converter used 10uF film capacitor, experiment was performed, and the efficiency of the proposed converter was measured with variable load and duty conditions.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권2호
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• pp.108-113
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• 2013

This paper describes a low power asynchronous successive approximation register (SAR) type 12b analog-to-digital converter (ADC) for biomedical applications in a 0.35 ${\mu}m$ CMOS technology. The digital-to-analog converter (DAC) uses a capacitive split-arrays consisting of 6-b main array, an attenuation capacitor C and a 5-b sub array for low power consumption and small die area. Moreover, splitting the MSB capacitor into sub-capacitors and an asynchronous SAR reduce power consumption. The measurement results show that the proposed ADC achieved the SNDR of 68.32 dB, the SFDR of 79 dB, and the ENOB (effective number of bits) of 11.05 bits. The measured INL and DNL were 1.9LSB and 1.5LSB, respectively. The power consumption including all the digital circuits is 6.7 ${\mu}W$ at the sampling frequency of 100 KHz under 3.3 V supply voltage and the FoM (figure of merit) is 49 fJ/conversion-step.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권2호
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.1146-1147
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• 2008

PV Power Conditioning System (PCS) must have high conversion and low cost. Generally, PV PCS uses either a single converter or multilevel module integrated converter (MIC). Each of these approaches has both advantage and disadvantage. For a high conversion efficiency and low cost of PV module, this paper proposes series connection of module integrated DC-DC converter's output with PV panel. Output voltage of PV panel is connected to the output capacitor of flyback converter. Thus, converter's output voltage is added to the output voltage of PV panel. Isolated DC-DC converter generates only the difference voltage between the PV panel voltage and the required total output voltage. This method reduces power level of DC-DC converter and enhances the energy conversion efficiency compared with conventional DC-DC converter.

• International journal of advanced smart convergence
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• 제10권1호
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.