• Journal of information and communication convergence engineering
• /
• v.5 no.1
• /
• pp.59-63
• /
• 2007

In this paper, a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Journal of information and communication convergence engineering
• /
• v.5 no.2
• /
• pp.131-135
• /
• 2007

In this paper, The proposed algorithm consists of three steps. In the first step, TD(Transition Density) calculation has to be performed. a CLB-based CPLD low-power technology mapping algorithm considered a Trade-off is proposed. To perform low-power technology mapping for CPLDs, a given Boolean network has to be represented in a DAG. Total power consumption is obtained by calculating the switching activity of each node in a DAG. In the second step, the feasible clusters are generated by considering the following conditions: the number of inputs and outputs, the number of OR terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low-power technology mapping based on the CLBs packs the feasible clusters. The proposed algorithm is examined using SIS benchmarks. When the number of OR terms is five, the experiment results show that power consumption is reduced by 30.73% compared with TEMPLA, and by 17.11 % compared with PLA mapping.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1165-1168
• /
• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. Therefore the proposed algorithm is proved an efficient algorithm for a low power CPLD technology mapping.

• Journal of Korea Society of Digital Industry and Information Management
• /
• v.4 no.3
• /
• pp.77-83
• /
• 2008

In this paper, CPLD low power technology mapping for reuse module design under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource. Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• Journal of the Korea Society of Computer and Information
• /
• v.11 no.3
• /
• pp.161-166
• /
• 2006

In this paper, CPLD low power technology mapping using reuse module selection under the time constraint is proposed. Traditional high-level synthesis do not allow reuse of complex, realistic datapath component during the task of scheduling. On the other hand, the proposed algorithm is able to approach a productivity of the design the low power to reuse which given a library of user-defined datapath component and to share of resource sharing on the switching activity in a shared resource Also, we are obtainable the optimal the scheduling result in experimental results of our using chaining and multi-cycling in the scheduling techniques. Low power circuit make using CPLD technology mapping algorithm for selection reuse module by scheduling.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1169-1172
• /
• 2003

In this paper, a CLB-based CPLD low-power technology mapping algorithm consider area and delay time is proposed. To perform low power technology mapping for CPLD, a given Boolean network have to be represented to DAG. The proposed algorithm are consist of three step. In the first step, TD(Transition Density) calculation have to be performed. In the second step, the feasible clusters are generated by considering the following conditions: the number of output, the number of input and the number of OR-terms for CLB(Common Logic Block) within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. In the final step, low power technology mapping based on the CLBs is packing the feasible clusters into the several proper CLBs. The proposed algorithm is examined by using benchmarks in SIS. In the case of that the number of OR-terms is 5, the experiments results show that reduce the power consumption by 30.73% comparing with that of TEMPLA, and 17.11% comparing with that of PLAmap respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.8
• /
• pp.84-91
• /
• 2002

In this paper, we proposed a CLB-based CPLD technology mapping algorithm for power minimization under time constraint in combinational circuit. The main idea of our algorithm is to exploit the "cut enumeration and feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. In our technology mapping algorithm conducted a low power by calculating TD and EP of each node and decomposing them on the circuit composed of DAG. It also takes the number of input, output, and OR-term into account on condition that mapping can be done up to the base of CLB, and so it generates the feasible clusters to meet the condition of time constraint. Of the feasible clusters, we should first be mapping the one that h3s the least output for technology mapping of power minimization and choose to map the other to meet the condition of time constraint afterwards. To demonstrate the efficiency of our approach, we applied our algorithm to MCNC benchmarks and compared the results with those of the exiting algorithms. The experimental results show that our approach is shown a decrease of 46.79% compared with DDMAP and that of 24.38% for TEMPLA in the power consumption.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.4
• /
• pp.215-220
• /
• 2007

Leakage current of CMOS circuits has become a major factor in VLSI design these days. Although many circuit-level techniques have been developed, most of them require significant amount of designers' effort and are not aligned well with traditional VLSI design process. In this paper, we focus on technology mapping, which is one of the steps of logic synthesis when gates are selected from a particular library to implement a circuit. We take a radical approach to push the limit of technology mapping in its capability of suppressing leakage current: we use a probabilistic leakage (together with delay) as a cost function that drives the mapping; we consider pin reordering as one of options in the mapping; we increase the library size by employing gates with larger gate length; we employ a new flipflop that is specifically designed for low-leakage through selective increase of gate length. When all techniques are applied to several benchmark circuits, leakage saving of 46% on average is achieved with 45-nm predictive model, compared to the conventional technology mapping.

• Journal of the Korea Society of Computer and Information
• /
• v.10 no.2 s.34
• /
• pp.49-57
• /
• 2005

In this paper. a CLB-based CPLD low power technology mapping algorithm for trade-off is proposed. To perform low power technology mapping for CPLD, a given Boolean network has to be represented to DAG. The proposed algorithm consists of three step. In the first step, TD(Transition Density) calculation have to be Performed. Total power consumption is obtained by calculating switching activity of each nodes in a DAG. In the second step, the feasible clusters are generated by considering the following conditions : the number of output. the number of input and the number of OR-terms for CLB within a CPLD. The common node cluster merging method, the node separation method, and the node duplication method are used to produce the feasible clusters. The proposed algorithm is examined by using benchmarks in SIS. In the case that the number of OR-terms is 5, the experiments results show reduction in the power consumption by 30.73$\%$ comparing with that of TEMPLA, and 17.11$\%$ comparing with that of PLAmap respectively

• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.361-364
• /
• 2002

In this paper, we consider the problem of CLB based CPLD technology mapping for power minimization in combinational circuit. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm for it. The main idea of our algorithm is to exploit the "cut enumeration" and "feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. However, for the consideration of both run time and memory space, only a fixed-number of solutions are selected and stored by our algorithm. To facilitate the selection process, a method that correctly calculates the estimated power consumption for each mapped sub-circuit is developed. The experimental results show that our approach is shown a decrease of 30.5% compared with DDMAP and that of 15.63% for TEMPLA in the Power consumption.