Low Power CPLD Technology Mapping Algorithm for FLEX10K series

FLEX10K 계열에 대한 저전력 CPLD 기술 매핑 알고리즘

In this paper, we consider the problem of CLB based CPLD technology mapping for power minimization in combinational circuit. The problem has been previously proved to be NP-hard, and hence we present an efficient heuristic algorithm for it. The main idea of our algorithm is to exploit the "cut enumeration" and "feasible cluster" technique to generate possible mapping solutions for the sub-circuit rooted at each node. However, for the consideration of both run time and memory space, only a fixed-number of solutions are selected and stored by our algorithm. To facilitate the selection process, a method that correctly calculates the estimated power consumption for each mapped sub-circuit is developed. The experimental results show that our approach is shown a decrease of 30.5% compared with DDMAP and that of 15.63% for TEMPLA in the Power consumption.