참고문헌
- The MACH 4 Family Data Sheet, Advanced Micro Devices, 1996
- S. Devadas, S. malik, 'A Survey of Optimization Techniques Targeting Low Power VLSI Circuits', in Proc. 32nd DAC, pp. 242-247, June 1995 https://doi.org/10.1145/217474.217536
- A. Chandrakasan, T. Sheng, and R. Brodersen, 'Low Power CMOS Digital Design', Journal of Solid State Circuits, vol. 27, no. 4, pp. 473-484, April 1992 https://doi.org/10.1109/4.126534
- S. Chakravarty, 'On complexity of using BDDs for the synthesis and analysis of boolean circuits', in Proc. 27th Annual Allerton Conf. On Communication Control and computing., pp. 730-739.1989
- S. ErColani et al., 'Testability measures in pseudorandom testing', IEEE Trans. Conputer-Aided Design., vol. 11, pp. 794-800, 1992, June https://doi.org/10.1109/43.137524
- J. Cong and Y. Ding, 'FlowMap : An 'Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs', IEEE Transactions on Computer Aided Design of Integrated Circuit and Systems, Vol. 13, No. 1, January 1994, pp. 1-11 https://doi.org/10.1109/43.273754
- R.J. Francis, J. Rose and Z. Vranestic, 'Chortle-crf : Fast Technology Mapping for Lookup Table-Based FPGAs', 28th ACM/IEEE Design Automation Conference, June 1991, pp. 227-233 https://doi.org/10.1145/127601.127670
- Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang, 'Power Minimization in LUT-Based FPGA Technology Mapping', ASP-DAC, pp. 635-640, January 2001 https://doi.org/10.1109/ASPDAC.2001.913380
- A. H. Farrahi and M. Sarrafzadeh, 'FPGA Technology Mapping for Power Minimization', Proc. Int. Workshop on field Programmable Logic and Applications, pp. 66-77, 1994
-
C. -C. Wang and C. -P. Kwan, 'Low Power Technology
https://doi.org/10.1109/ISCAS.1997.621421 - R.J.Francis, J. Rose and Z. Vranestic, 'Technology Mapping of Lookup Table-Based FPGAs for Performance', 1991 IEEE Conference on Computer Aided Design, pp. 568-571 https://doi.org/10.1109/ICCAD.1991.185334
- E. M. Sentovice et al., 'SIS : A system for sequential Circuit Synthesis', Technocal Report UCM/ERL M92/41, Electronics Research Laboratory, Departmant of Electrical Engineering and Computer Science, University of California, Berkeley, 1992
- Jason Helge Anderson, Stephen Dean Brown, 'Technology Mapping for Large Complex PLDs', Design Automation Conference, 1998, pp. 698-703 https://doi.org/10.1145/277044.277220
- Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin, 'A New Technology Mapping for CPLD under the time constraint' ASP-DAC, pp. 235-238, January 2001 https://doi.org/10.1109/ASPDAC.2001.913311