• Journal of IKEEE
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• v.23 no.2
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• pp.552-556
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• 2019

This paper present a capless low drop out regulator (LDO) that improves the load transient response characteristics by using a current regulator. A voltage regulator circuit is placed between the error amplifier and the pass transistor inside the LDO regulator to improve the current characteristics of the voltage line, The proposed fast transient LDO structure was designed by a 0.18 um process with cadence's virtuoso simulation. according to test results, the proposed circuit has a improved transient characteristics compare with conventional LDO. the simulation results show that the transient of rising increases from 1.954 us to 1.378 us and the transient of falling decreases from 19.48 us to 13.33 us compared with conventional capless LDO. this Result has improved response rate of about 29%, 28%.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.313-319
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• 2012

The power supply rejection (PSR) of low drop-out (LDO) voltage regulator is improved by employing an error amplifier (EA) which is configured so the power supply noise be cancelled at the output. The LDO regulator is implemented in a 0.13-${\mu}m$ standard CMOS technology. The external supply voltage level is 1.2-V and the output is 1.0-V while the load current can range from 0-mA to 50-mA. The power supply rejection is 46-dB, 49-dB, and 38-dB at DC, 2-MHz, and 10-MHz, respectively. The quiescent current consumption is 65-${\mu}A$.

• Journal of IKEEE
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• v.24 no.2
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• pp.598-603
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• 2020

In this paper present a Low Drop-Out(LDO) regulator that improves load transient characteristics due to the push-pull pass transistor structure is proposed. Improved load over the existing LDO regulator by improving the overshoot and undershoot entering the voltage line by adding the proposed push-pull circuit between the output stage of the error amplifier inside the LDO regulator and the gate stage of the pass transistor and the push-pull circuit at the output stage. It has a delta voltage value of transient characteristics. The proposed LDO structure was analyzed in Samsung 0.13um process using Cadence's Virtuoso, Spectre simulator.

• Journal of IKEEE
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• v.23 no.2
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• pp.722-726
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• 2019

In this paper, we propose a low drop-out (LDO) regulator with improved power-supply rejection (PSR) characteristics in the high frequency region. In particular, an NMOS transistor with a high output resistance is added as a compensation circuit to offset the high frequency noise passing through the finite output resistance of the PMOS power switch. The elimination of power supply noise by the compensating transistor was explained analytically and presented as the direction for further improvement. The circuit was fabricated in a $0.35-{\mu}m$ standard CMOS process and Specter simulations were carried out to confirm the PSR improvement of 26 dB compared to the conventional LDO regulator at 10 MHz.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.937-940
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• 2005

In this paper, the design of high current and high performance Regulatior IC using BCD Technology are presented. We design the 5A class regulator IC including the VDMOS Pass Tr. of N-sink array structure. Also, to obtain the high current and low power characteristics, the PMOS and BJT device are adapted for the Pass Tr. It is shown that simulation results of Regulator IC with VDMOS Pass Tr. have the Iout=4.5092A, LDO=7.3mV.

• Journal of IKEEE
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• v.21 no.3
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• pp.264-267
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• 2017

In this paper, A low dropout (LDO) regulator that improves the power supply rejection ratio by using a noise canceling circuit is proposed. The noise rejection circuit between the error amplifier and the pass transistor is designed to reduce the influence of the pass transistor on the noise coming from the voltage source. The LDO regulator has the same regulation characteristics as the conventional LDO regulator. The proposed circuit uses 0.18um process and Cadence's Virtuoso and Specter simulator.

• Journal of IKEEE
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• v.27 no.3
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• pp.258-264
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• 2023

This paper proposes an LDO regulator with a built-in ESD (Electro Static Discharge) protection circuit to effectively operate and prevent destruction of the LDO (Low Drop Out) regulator according to the load current. The proposed LDO regulator can more effectively adjust the gate node voltage of the pass transistor according to the output voltage of the LDO regulator by using an additional feedback current circuit structure. In addition, it is expected to have high reliability for the ESD situation by embedding a new structure that increases the holding voltage by about 2V by reducing the current gain on the SCR loop by adding a P+ bridge to the existing ESD protection device.

• ETRI Journal
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• v.39 no.3
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• pp.373-382
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• 2017

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).

• Journal of IKEEE
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• v.19 no.3
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• pp.304-310
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• 2015

A SCALDO(Supercapacitor Assisted LDO) regulator is a new regulator having advantages of a SMPS(Switch Mode Power Supply) which has a good efficiency and a LDO(Low Drop-out) regulator which has stable output characteristics and good EMI(Electro Magnetic Interference) characteristics. However, a conventional SCALDO regulator needs a lot of power consumption to control its switches and it drops an efficiency of the circuit. In this paper, to reduce switching power consumption and improve an efficiency of the circuit, a new SCALDO regulator adopting MOSFETs as its switching parts is proposed and it is found out that the proposed SCALDO regulator has the maximum 9.5% higher efficiency than the conventional SCALDO regulator. We also try to simplify production process of the circuit by changing switching control method of the circuit from MCU(Micro-controller unit) based firmware control to hardware control using a comparator and a T-F/F(Flip Flop).

• Journal of IKEEE
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• v.22 no.2
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• pp.384-392
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• 2018

A multiple-output LDO regulator is a good choice in terms of the efficiency in embedded systems requiring various supply voltages. A small feedback factor in LDO incurs the long settling time, resulting in large ripples in the time-multiplexing strategy. A new proposed topology enhances the settling time, and hence the ripples by incorporating the constant feedback factor with different reference voltages. The simulation results of a prototype design in a standard $0.35{\mu}m$ CMOS process verify that the proposed strategy enhances the settling time and ripple characteristic by more than doubled than a conventional circuit using the feedback factor of less than 0.4.