• Industrial Engineering and Management Systems
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• v.8 no.3
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• pp.171-180
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• 2009

Population learning algorithm (PLA) is a population-based method that was inspired by the similarities to the phenomenon of social education process in which a diminishing number of individuals enter an increasing number of learning stages. The study aims to develop a framework that repeatedly applying the PLA to solve the discrete resource constrained project scheduling problem with two objectives: minimizing project makespan and renewable resource availability, which are two most common concerns of management when a project is being executed. The PLA looping framework will provide a number of near Pareto optimal schedules for the management to make a choice. Different improvement schemes and learning procedures are applied at different stages of the process. The process gradually becomes more and more sophisticated and time consuming as there are less and less individuals to be taught. An experiment with ProGen generated instances was conducted, and the results demonstrated that the looping framework using PLA outperforms those using genetic local search, particle swarm optimization with local search, scatter search, as well as biased sampling multi-pass algorithm, in terms of several performance measures of proximity. However, the diversity using spread metric does not reveal any significant difference between these five looping algorithms.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.2 no.4
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• pp.61-66
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• 2003

An excellent mesh construction is of Importance in yielding good results of finite element analysis. The new mesh generation algorithm, which offsets boundaries inward, was developed on the basis of a looping method. An user interface technique and automatic splitting lines which both divide a given domain into subdomains manually or automatically, were used. In addition, the separation method has advantages to prevent the large scale of element size and to control numbers of nodes and elements. This new mesh generation algorithm was proved in practice.

• Transactions of the Korean Society of Mechanical Engineers
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• v.18 no.11
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• pp.2932-2943
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• 1994

An efficient approach to the automatic construction of effective quadrilateral finite element meshes for two-dimensional analysis is presented. The procedure is composed of, firstly, an initial mesh generation and, secondly, an h-version of adaptive refinement based on error analysis. As for an initial mesh generation scheme, a modified looping algorithm has been employed. For the adaptive refinement process, an error indicator obtained by computing the residual error of the equilibrium equations in the energy norm with a relaxation factor has been employed. Examples of mesh generation and self-adaptive mesh improvements are given. These example solutions demonstrate that an effective mesh for a given error tolerance can be obtained in a few steps of the analysis processes.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.4
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• pp.148-155
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• 1996

A loop structure optimization algorithm is proposed for generting a set of efficient codes for loop structure in order to optimize RISC compiler codes. Since there are so many loop structure in the program, most of the execution time is used to process looping codes. Thus, reduction of loop instructions is more effective than optimizing codes outside the loop. The proposed algorithm presents a method to combine several different loops into a simple loop. Therefore, rather than executing each loop independently, loops in the program are serached, analyzed, and finally created some relative informtion such as dependency and range. In doing so, the loops in the program can efficiently be recombined and restructured. As a result, the overall execution time for the program of the sequential programming language is reduced.

• Transactions of the Korean Society of Mechanical Engineers
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• v.17 no.12
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• pp.2995-3006
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• 1993

An automatic mesh generation scheme has been developed for finite element analysis with two-dimensional, quadrilateral elements. The basic strategies of the method are to transform the analysis domain into loops with key nodes and the loops are recursively subdivided into subloops with the use of best split lines. Finally by using the basic loop operators, the meshes are completed. In this algorithm an eight-node loop operator is proposed, which is useful in the area where the change of element size is large and the splitting criteria for subdividing the loops have also been modified to the existing algorithms. Lines, arcs, and cubic spline curves are used to define the boundaries of analysis domain. Sample meshes for several geometries are presented to demonstrate the robustness of the algorithm.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.19 no.6
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• pp.63-70
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• 2009

Many research results show that RSA system mounted using conventional binary exponentiation algorithm is vulnerable to some physical attacks. Recently, Schmidt and Hurbst demonstrated experimentally that an attacker can exploit secret key using faulty signatures which are obtained by skipping the squaring operations. Based on similar assumption of Schmidt and Hurbst's fault attack, we proposed new fault analysis attacks which can be made by skipping the multiplication operations or computations in looping control statement. Furthermore, we applied our attack to Montgomery ladder exponentiation algorithm which was proposed to defeat simple power attack. As a result, our fault attack can extract secret key used in Montgomery ladder exponentiation.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.121-128
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• 1997

This paper proposes a class of rearrangeable networks, called generalized rearrangeable networks(GRNs). GRNs are obtained from the Benes network by rearranging the connections between states and the switches within each stage. The GRNs constitute all of the rearrangeable networks which have the recursive decomposition structure and can be routed by the outside-in decomposition of permutations as the Bene network. This paper also presents a necessary condition for a network to be a GRN and a network labeling scheme to check if a network satisfies the condition. the general routing algorithm for the GRNs is given by modifying slightly the looping algorithm of the Benes network.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.

• Journal of KIISE:Computing Practices and Letters
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• v.13 no.4
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• pp.231-239
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• 2007

This paper presents the trade-off relationship between area and performance in the hardware design space exploration for the Korean national standard 128-bit block cipher algorithm SEED. In this paper, we compare the following four hardware design types of SEED algorithm : (1) Design 1 that is 16 round fully pipelining approach, (2) Design 2 that is a one round looping approach, (3) Design 3 that is a G function sharing and looping approach, and (4) Design 4 that is one round with internal 3 stage pipelining approach. The Design 1, Design 2, and Design 3 are the existing design approaches while the Design 4 is the newly proposed design in this paper. Our new design employs the pipeline between three G-functions and adders consisting of a F function, which results in the less area requirement than Design 2 and achieves the higher performance than Design 2 and Design 3 due to pipelining and module sharing techniques. We design and implement all the comparing four approaches with real hardware targeting FPGA for the purpose of exact performance and area analysis. The experimental results show that Design 4 has the highest performance except Design 1 which pursues very aggressive parallelism at the expanse of area. Our proposed design (Design 4) shows the best throughput/area ratio among all the alternatives by 2.8 times. Therefore, our new design for SEED is the most efficient design comparing with the existing designs.

• Korean Journal of Computational Design and Engineering
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• v.1 no.3
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• pp.224-233
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• 1996

An automatic mesh generation scheme with triangular finite elements on three-dimensional surfaces has been developed. The surface triangulation process is performed as follows. To begin, surfaces with key nodes are transformed to two-dimensional planes and the meshes with triangular elements are constructed in these planes. Finally, the constructed meshes are transformed back to the original 3D surfaces. For the mesh generation, an irregular mesh generation scheme is employed in which local mesh densities are assigned by the user along the boundaries of the analysis domain. For this purpose a looping algorithm combined with an advancing front technique using basic operators has been developed, in which the loops are recursively subdivided into subloops with the use of the best split lines and then the basic operators generate elements. Using the split lines, the original boundaries are split recursively until each loop contains a certain number of key nodes, and then using the basic operators such as type-1 and type-2, one or two triangular elements are generated at each operation. After the triangulation process has been completed for each meshing domain, the resulting meshes are finally improved by smoothing process. Sample meshes are presented to demonstrate the versatility of the algorithm.