• Journal of the Korea Society for Simulation
• /
• v.3 no.1
• /
• pp.107-114
• /
• 1994

This paper describes an integrated environment for logic circuit simultion which is an important step of logic circuit design. The system consists of a logic simulator kernel, an expandible element routine library. a functional level element routine generator, several HDL input parsers, and a postprocessor. The system can simulate the same system in several levels of hierarchy. The experimental result shows that the system is very efficient and useful for design of logic circuits.

• Journal of Practical Engineering Education
• /
• v.9 no.1
• /
• pp.41-48
• /
• 2017

In this paper, we proposed a method for digital logic circuit control, through arduino device programming with digital outputs, to design a curriculum for basic digital logic circuit practices. Curricula for arduino device programming and digital logic circuit are essentially practiced in engineering departments of colleges or high schools in South Korea. However, actual practice course lacks the experimental examples of digital logic circuit combined with arduino device programming. Furthermore, actual practice course lacks the curriculum in that students design and test their own digital logic circuits with the less cost than the oscilloscope. Therefore, to solve these problems in this paper, we proposed a curriculum for basic digital logic circuit practices during one semester. In this curriculum, students control and experiment their own digital logic circuits through arduino device programming with digital outputs.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.30B no.11
• /
• pp.1-10
• /
• 1993

This paper proposes a High Performance Full-Swing BiCMOS (HiF-BiCMOS) circuit which improves on the conventional BiCMOS circuit. The HiF-BiCMOS circuit has all the merits of the conventional BiCMOS circuit and can realize full-swing logic operation. Especially, the speed of full-swing logic operation is much faster than that of conventional full-swing BiCMOS circuit. And the number of transistors added in the HiF-BiCMOS for full-swing logic operation is constant regardless of the number of logic gate inputs. The HiF-BiCMOS circui has high stability to variation of environment factors such as temperature. Also, it has a preamorphized Si layer was changed into the perfect crystal Si after the RTA. Remarkable scalability for power supply voltage according to the development of VLSI technology. The power dissipation of HiF-BiCMOS is very small and hardly increases about a large fanout. Though the Spice simulation, the validity of the proposed circuit design is proved.

• Proceedings of the KIEE Conference
• /
• 1988.07a
• /
• pp.574-578
• /
• 1988

This paper proposes testable design method of Domino CMOS NOR-NOR Array Logic design method. Previous Domino CMOS PLA method is composed of 2 level NAND-NAND Logic. Because NOR-NOR Logic is realized by a parallel circuit, this method can prevent delay time each level and DNOR-PLA include testable circuit system that DNOR-PLA circuit. DNOR-PLA testable algorithm is realized on Prime (Primos) in Pascal language and DNOR-PLA circuit is simulated by PSPICE.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.191-194
• /
• 2000

A level of integration will increase, if the number of elements of the circuit can be reduced. We aim to design the circuit of the new system for any further integration by using Neuron MOS Transistor. In this paper, we consider to introduce Soft-Hardware Logic and multiple-valued logic to the design methods for reducing the number of elements and inner wiring. We have designed 4-valued add-subtracter circuit using above logic. We discuss the design methods, features, and characteristics of this circuit by SPICE simulation.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.9 no.1
• /
• pp.89-94
• /
• 2009

This paper proposes the algorithms that design the highly digital logic circuit and assign the code to each node of DCG(Directed Cyclic Graph) of length ${\zeta}$. The conventional algorithm have some problems, so this paper introduce the matrix equation from DCG of length ${\zeta}$ and proposes highly digital logic circuit design algorithms according to the DCG of length ${\zeta}$. Using the proposed circuit design algorithms in this paper, it become realized that was able to design from former algorithm. Also, making a comparison between the circuit using former algorithm and this paper's, we testify that proposed paper's algorithm is able to realize more optimized circuit design. According to proposed circuit design algorithm in this paper, it is possible to design current that DCG have natural number, so it have the following advantages, reduction of the circuit input/output digits, simplification of circuit composition, reduction of computation time and cost. And we show comparability and verification about this paper's algorithm.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.37 no.6
• /
• pp.42-49
• /
• 2000

In this paper, we propose the parallel ternary logic circuit design algorithm to DCG Property with 2$^n$ nodes. To increase circuit integration, one of the promising approaches is the use of multiple-valued logic(MVL). It can be useful methods for the realization of compact integrated circuit, the improvement of high velocity signal processing using parallel signal transmission and the circuit design algorithm to optimize and satisfy the circuit property. It is all useful method to implement high density integrated circuit. In this paper, we introduce matrix equation to satisfy given DCG with 2$^n$ nodes, and propose the parallel ternary logic circuit design process to circuit design algorithm. Also, we propose code assignment algorithm to satisfy for the given DCG property. According to the simulation result of proposed circuit design algorithm, it have the following advantage ； reduction of the circuit signal lines, computation time and costs.

• Proceedings of the KIEE Conference
• /
• 2005.05a
• /
• pp.148-151
• /
• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• 한국초전도학회:학술대회논문집
• /
• 2007.07a
• /
• pp.22-23
• /
• 2007

• The Transactions of the Korean Institute of Electrical Engineers
• /
• v.33 no.4
• /
• pp.134-139
• /
• 1984

This paper presents the computer program to design the synchronous sequential logic circuit. The computer program uses the MASK method to get the circuit of optimal cost. The computer program takes as an input, the minimal reduced state transition table where each state has its internal code. As an output,the optimal design of synchronous sequential logic circuit is generated for each flipflop type of JK,T,D, and RS respectively. And these circuits for 4 flipflop types are evaluated and sorted in ascending order of their costs, so that the user can select the proper flipflop type and its circuit. Furthermore,the proposed computer program may be applied to state assignment with its facility of cost evaluation.