• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.8
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• pp.807-813
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• 2008

The gate-biases of the Doherty power amplifier are controlled to improve the linearity performance. The linearity improvement mechanism of the Doherty amplifier is the harmonic cancellation of the carrier and peaking amplifier at the output power combining point. However, it is difficult to cancel the harmonic power for the broader power range because the condition for cancelling is varied by power. For the linearity improvement, we have explored the linearity characteristic of the Doherty amplifier according to the input power and gate biases of the carrier and peaking amplifier. To extend the region of harmonic power cancellation, we have injected the proper gate bias to the carrier and peaking amplifier according to the input power levels. To validate the linearity improvement, the Doherty amplifier is designed using Eudyna 10-W PEP GaN HEMT EGN010MKs at 2.345 GHz and optimized to achieve a high linearity and efficiency at an average output power of 33 dBm, backed off about 10 dB from the $P_{1dB}$. In the experiments, the envelope tracking Doherty amplifier delivers a significantly improved adjacent channel leakage ratio performance of -37.4 dBc, which is an enhancement of about 2.8 dB, maintaining the high PAE of about 26 % for the WCDMA 1-FA signal at an average output power of 33 dBm. For the 802.16-2004 signal, the amplifier is also improved by about 2 dB, -35 dB.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.547-548
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• 2008

Linearity improvement technique of transconductor is presented in the paper. In order to certify the linearity improvement of proposed transconductor, the 3rd-order Elliptic low-pass Gm-C filter which provides 5MHz cutoff is implemented by using the transconductor. According to the IIP3 measurement result of filters, proposed filter has higher IIP3 than normal source-degeneration filter; the In-band IIP3 of proposed and normal filter are 10.1 dBm and 7.5 dBm respectively. The filter is fabricated in 1P6M $0.18-{\mu}m$ CMOS while consuming the 3.3mW with 1.8 Vdd. The in-band input-referred noise voltage is $62.3{\mu}Vrms$ and the SFDR is 54.1 dB.

• IEIE Transactions on Smart Processing and Computing
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• v.3 no.4
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• pp.161-166
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• 2014

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

• JSTS:Journal of Semiconductor Technology and Science
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• v.2 no.1
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• pp.30-40
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• 2002

A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.7 no.2
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• pp.62-69
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• 2008

This paper proposes linearization technique that the linearity is improved by controlling IMD between the drive stage and the output stage. From the experimental results of W-CDMA 4FA input signal, this amplifier has ACLR of -48dBc@5MHz offset at 50W average power. Proposed linearization technique provides predistortion effect for using drive amplifier without additional circuit, which is the significant in this paper that it makes up for the weak point of analog predistortion method and feedforward method.

• Journal of Multimedia Information System
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• v.8 no.1
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• pp.45-56
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• 2021

This document traces the new technologies development based on a deep classical Hill method improvement. Based on the chaos, this improvement begins with the 256 element body construction, which is to replace the classic ring used by all encryption systems. In order to facilitate the application of algebraic operators on the pixels, two substitution tables will be created, the first represents the discrete logarithm, while the second represents the discrete exponential. At the same time, a large invertible matrix whose structure will be explained in detail will be the subject of the advanced classical Hill technique improvement. To eliminate any linearity, this matrix will be accompanied by dynamic vectors to install an affine transformation. The simulation of a large number of images of different sizes and formats checked by our algorithm ensures the robustness of our method.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.403-408
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• 2008

In this paper, the high efficiency and linearity Doherty power amplifier using DGS and adaptive bias technique has been designed and realized for 2.3GHz WiBro applications. The Doherty amplifier has been implemented us-ing silicon MRF 281 LDMOS FET. The RF performances of the Doherty power amplifier (a combination of a class AB carrier amplifier and a bias-tuned class C peaking amplifier) have been compared with those of a class AB amplifier alone, and conventional Doherty amplifier. The Maximum PAE of designed Doherty power amplifier with DGS and adaptive bias technique has been 36.6% at 34.01dBm output power. The proposed Doherty power amplifier showed an improvement 1dB at output power and 7.6% PAE than a class AB amplifier alone.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• Journal of the Korean Society for Precision Engineering
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• v.13 no.6
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• pp.128-135
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• 1996

This paper proposes a high precision measurement technique to obtain the height of gage block with a few millimeter height. The proposed technique is consisted of two steps : In the first step, laser position transducer and electric micrometer are adopted to obtain a coarse value of the height of gage block, and then, in the second step, heterodyne laser interferometry is adopted to acquire the precision value. A new kind of phase detector is constructed in the low cost for the heterodyne interferometer and its linearity with ${\pm}1%$ is confirmed by experiment. Also measurement error factors due to enviroments are discussed and methodology to reduce such errors is proposed. Preliminary experiments are carried out for the gage blocks of as high as a few millimeter.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.8 no.1
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• pp.12-17
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• 2009

In this paper, We play it for the purpose of study about the power amplifier which applied DGS and adaptive bias circuit structure to general Doherty amplifier for the efficiency of a RF power amplifier and a linearity improvement in the WiBro band. As for the IMD3, 3.4dBc was improved with -26.3dBc when we did the measurement result existing Doherty power amplifier and comparison of the Doherty power amplifier which applied an adaptive bias circuit and the DGS which proposed in this paper, and the mean power efficiency verified what was increased in 37%. Also, we were able to know PAE of 36.6% with output power 34.0dBm in P1dB when magnitude of an input signal was 25.6dBm. we did 6dB back off in output P1dB in order to confirm the ACPR which was a nonlinear characteristic and measured the ACPR. we showed the -34.55dBc which was a value of -34.5dBc or below in the 4.77MHz off-set that was a transmission standard. Therefore, we were able to know that we were satisfied with a spectrum mask standard.