IEIE Transactions on Smart Processing and Computing

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A Capacitor Mismatch Error Cancelation Technique for High-Speed High-Resolution Pipeline ADC

  • Park, Cheonwi (School of Mechatronics, Gwangju Institute of Science and Technology) ;
  • Lee, Byung-Geun (School of Mechatronics, Gwangju Institute of Science and Technology)
  • Received : 2013.12.20
  • Accepted : 2014.05.12
  • Published : 2014.08.31
Download PDF
⟨ Previous Next ⟩

Abstract

An accurate gain-of-two amplifier, which successfully reduces the capacitor mismatch error is proposed. This amplifier has similar circuit complexity and linearity improvement to the capacitor error-averaging technique, but operates with two clock phases just like the conventional pipeline stage. This makes it suitable for high-speed, high-resolution analog-to-digital converters (ADCs). Two ADC architectures employing the proposed accurate gain-of-two amplifier are also presented. The simulation results show that the proposed ADCs can achieve 15-bit linearity with 8-bit capacitor matching.

Keywords

References

  1. K. Bult and G. Geelen, "A fast-settling CMOS opamp for SC circuits with 90-dB DC gain", IEEE J. Solid-State Circuits, vol. 25, pp. 1379-1384, December. 1990. https://doi.org/10.1109/4.62165
  2. Y.Chiu, P.R. Gray and B. Nikolic, "A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR", IEEE J. Solid-State Circuits, vol. 39, pp. 2139-2151, December. 2004. https://doi.org/10.1109/JSSC.2004.836232
  3. S. H. Lewis and P.R. Gray, "A pipelined 5-Msample/s 9-bit analog-to-digital converter", IEEE J. Solid-State Circuits, vol. 22, pp. 954-961, December. 1987. https://doi.org/10.1109/JSSC.1987.1052843
  4. H.-S. Lee, D. Hodges and P.R. Gray, "A selfcalibrating 12b 12${\mu}$s CMOS ADC", ISSCC Dig. Tech. Papers, pp. 64-66, Feb. 1984.
  5. Y.M. Lin, B. Kim and P.R. Gray, "A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-${\mu}$m CMOS", IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, April. 1991. https://doi.org/10.1109/4.75065
  6. U.-K. Moon and B.-S. Song, "Background Digital Calibration Techniques for Pipelined ADC's ", IEEE J. Solid-State Circuits, vol. 44, pp. 102-109, February. 1997.
  7. J. Guo, W. Law, W. J. Helms, and D. J. Allstot, Digital Calibration for Monotonic Pipelined A/D Converters, IEEE Trans. Instrum. Meas., vol. 53, pp. 1485-1492, Dec. 2004. https://doi.org/10.1109/TIM.2004.834080
  8. M. Furuta, S. Kawahito, and D. Miyazaki, A Digital-Calibration Technique for Redundant Radix-4 Pipelined Analog-to-Digital Converters, IEEE Trans. Instrum. Meas., vol. 56, pp. 2301-2311, Dec. 2007. https://doi.org/10.1109/TIM.2007.904569
  9. P.W. Li, M.J. chin, P.R. Gray, and R. Castello, "A Ratio-Independent Algorithmic Analog-to-Digital Conversion Technique", IEEE J. Solid-State Circuits, vol. 19, pp. 828-836, December. 1984. https://doi.org/10.1109/JSSC.1984.1052233
  10. P.C. Yu, and H.-S. Lee, "A 2.5-V, 12-b, 5-MSample/s Pipelined CMOS ADC", IEEE J. Solid-State Circuits, vol. 31, pp. 1854-1861, December. 1996. https://doi.org/10.1109/4.545805
  11. B.-S. Song, M.F. Tompsett and K.R. Lakshmikumar, "A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter", IEEE J. Solid-State Circuits, vol. 23, pp. 1324-1333, December. 1988. https://doi.org/10.1109/4.90028
  12. H.-S. Chen, B.-S. Song, and K. Bacrania, "A 14-bit 20-Msample/s CMOS pipelined ADC", IEEE J. Solid-State Circuits, vol. 36, pp. 997-1001, June. 2001. https://doi.org/10.1109/4.924862
  13. H.-C. Kim, D.-K. Jeong and Wonchan. Kim, "A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique", ISSCC Dig. Tech. Papers, pp. 284-598 Feb. 2005.
  14. C.S.G. Conroy, D.W. Cline and P.R. Gray, "An 8-b 85-MS/s parallel pipeline A/D converter in 1-${\mu}$m CMOS", IEEE J. Solid-State Circuits, vol. 28, pp. 447-454, April. 1993. https://doi.org/10.1109/4.210027
  15. O. Stoeble, V. Dias and C. Schwoerer, "An 80 MHz 10 b pipeline ADC with dynamic range doubling and dynamic reference selection", ISSCC Dig. Tech. Papers, pp. 462-539, Feb. 2004.
  16. Byung-Moo Min. P. Kim, F.W. Bowman, D.M. Boisvert, A.J. Aude, "A 69-mW 10-bit 80-MSample/s Pipelined CMOS ADC", IEEE J. Solid-State Circuits, vol. 38, pp. 2031-2039, Dec. 2003. https://doi.org/10.1109/JSSC.2003.819166