• 대한전기학회논문지
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• 제38권6호
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• pp.401-415
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• 1989

A simple but accurate analytical model for the lateral channel electric field in gate-offset structured Lightly Doped Drain MOSFET has been developed. Our model assumes Gaussian doping profile, rather than simple uniform doping, for the lightly doped region and our model can be applied to LDD structures where the junction depth of LDD is not identical to the heavily doped drain. The validity of our model has been proved by comparing our analytical results with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field on the drain and gate bias conditions and process, design parameters. Advantages of our analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate/drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot-electron pohenomena, individually. Our model can also find the optimum doping concentration of LDD which minimizes the peak electric field and hot-electron effects.

• 대한전자공학회논문지
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• 제27권1호
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• pp.74-80
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• 1990

The transconductance of short channel LDD MOSFETs in the saturation region (high Vd)has shown different characteristics from that of conventional device. The transconductance in saturation regime of short channel LDD MOSFETs is reduced from maximum value at higher gate voltage. This decline is analyzed as the velocity saturation effects of carrier at LDD region but accurate analytical expressions for the drain current Idsat and the transconductance Gmsat in the saturation regime are still not in existence. Recently the drain current dependence of parasitic source resistance Rs has been modeled from the velocity saturation of carriers in LDD region. In this study, we approximate that Rmsat that Rs is linearly dependent on the applied gate voltage. Analytical expressions for Idsat and Gmsat obtained from this approximation show the same general behavior as experimental results of short channel LDD NMOSFETs.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1988년도 추계학술대회 논문집 학회본부
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• pp.363-367
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• 1988

A simple analytical model for the lateral channel electric field in gate - offset structured Lightly Doped Drain MOSFET has been developed. The model's results agree well with two dimensional device simulations. Due to its simplicity, our model gives a better understanding of the mechanisms involved in reducing the electric field in the LDD MOSFET. The model shows clearly the dependencies of the lateral channel electric field as function of drain and gate bias conditions and process, design parameters. Advantages of analytical model over costly 2-D device simulations is to identify the effects of various parameters, such as oxide thickness, junction depth, gate / drain bias, the length and doping concentration of the lightly doped region, on the peak electric field that causes hot - electron phenomena, individually. We are able to find the optimum doping concentration of LDD minimizing the peak electric field and hot - electron effects.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.825-828
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• 1992

In this paper, a Hybrid method for an effective channel length($L_{eff}$) on lightly doped drain(LDD) MOSFET's is proposed. In order to investigate the difference of the gate bias and substrate bias defendence of the $L_{eff}$ among various LDD structures, the $L_{eff}$ of the LDD's are extensively examined using simulations and measurement. one group is proposed for conventional MOSFET and the other group Is proposed for LDD MOSFET. It is shown that the $V_{bs}$-dependence of the n-region is different from $V_{gs}$-dependence of it.

• ETRI Journal
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• 제8권4호
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• pp.103-109
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• 1986

LDD(Lightly Doped Drain) 방식에 의한 MOSFET의 제조 공정 및 특성에 관하여 실험 분석하였다. MOS 소자의 채널 길이가 짧아짐에 따라 드레인 가장자리에서 자체 형성되는 높은 전계로 말미암아 애벌런치 항복 전압(avalanche breakdown voltage)이 상당히 감소 한다. 이 전압을 높여 주기 위한 기술로서 LDD 방식이 적용되었으며 종래의 제조방식에 의한 MOSFET와 비교 기술되었다.

• 한국세라믹학회지
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• 제38권10호
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• pp.871-875
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• 2001

Cobalt silicidation at sidewall spacer edge of Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) with post annealing treatment for capacitor forming process has been investigated as a function of dopant species. Cobalt silicidation of nMOSFET with n-type Lightly Doped Drain (LDD) and pMOSFET with p-type LDD produces a well-developed cobalt silicide with its lateral growth underneath the sidewall spacer. In case of pMOSFET with n-type LDD, however, a void is formed at the sidewall spacer edge with no lateral growth of cobalt silicide. The void formation seems to be due to a retarded silicidation process at the LDD region during the first Rapid Thermal Annealing (RTA) for the reaction of Co with Si, resulting in cobalt mono silicide at the LDD region. The subsequent second RTA converts the cobalt monosilicide into cobalt disilicide with the consumption of Si atoms from the Si substrate, producing the void at the sidewall spacer edge in the Si region. The void formed at the sidewall spacer edge serves as a resistance in the current-voltage characteristics of the pMOSFET device.

• 대한전자공학회논문지
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• 제24권3호
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• pp.478-485
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• 1987

Optimization of the sub-micron N-channel MOSFET with the LDD(Lightly Doped Drain)structure has been investigated. LDD devices with various length of n-region, n-dose and n-implantation species were fabricated for this purpose. It will be shown that LDD devices have lower substrate current by an order of magnitude and higher breakdown voltage than the conventional devices with comparable channel length. Optimized LDD structure has been found when the sidewall thickness is 2500\ulcorner and n-region is phosphorus implantd with the dose of 1.0E13/cm\ulcorner It has been found that transconductance degradation is less than 20%.

• 대한전자공학회논문지
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• 제27권11호
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• pp.49-54
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• 1990

본 논문에서는 LDD(lightly doped drain)구조를 갖는 짧은 채널 MOSFET에서의 기생저항의 게이트 전압 의존도에 대한 모형을 제시하였다. 게이트 전극 밑에 위치한 LDD 영역에서는 게이트 전압에 의해 준 이차원적인 축적층(quasi two-dimensional accumulation layer)이 형성된다. 소오스 측 LDD 기생저항을 축적층의 저항과 벌크 LDD 저항의 병렬 연결로 취급하였으며 별크 LDD 저항은 채널의 반전층 끝으로부터 ${n^+}$영역의 경계까지 퍼짐 저항으로 근사하였다. 그리고 접합에서의 도우핑 농도 구배가 LDD 저항에 미치는 영향이 토의하였다. 본 모형의 결과로 선형 영역에서는 LDD 저항이 게이트 전압의 증가에 따라 감소하고, 포화영역에서는 채널과 LDD에서 속도포화를 고려한 결과, 게이트 전압에 대해 준 일차적으로 증가하는 것으나 나타나 발표된 실험결과들과 일치하였다.

• 한국전기전자재료학회논문지
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• 제15권1호
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• pp.1-6
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• 2002

The hot carried degradation in a metal oxide semiconductor device has been one of the most serious concerns for MOS-ULSI. In this paper, three types of LDD(lightly doped drain) structure for suppression of hot carried degradation, such as decreasing of performance due to spacer-induced degradation and increase of series resistance will be investigated. in this study, LDD-nMOSFETs used had three different drain structure, (1) conventional surface type LDD(SL), (2) Buried type LDD(BL), (3) Surface implantation type LDD(SI). As experimental results, the surface implantation the LDD structure showed that improved hot carrier lifetime to comparison with conventional surface and buried type LDD structures.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.303-306
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• 2005

We report the self-aligned low temperature poly silicon (LTPS) TFT process using simple doping process. In conventional LTPS-TFT, the Lightly Doped Drain (LDD) doping and source/drain doping are processed separately by aligning the gate with the source and drain during the gate lithography step. This ne w process not only fabricates fully self-aligned low temperature poly silicon TFTs with symmetric LDD structure but also simplifies the process flow with combined source/drain doping and LDD doping in one step. LDD doping process can be achieved using only source/drain doping process according to the new structure. In this paper, the TFT characteristics of NMOS and PMOS using the new doping process will be discussed.