• Journal of the Korean Ceramic Society
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• v.49 no.6
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• pp.485-492
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• 2012

Dense and single phase $BiFeO_3$ (BFO) ceramics were prepared using attrition milled calcined (coarse) powders of an average particle size of ${\approx}3{\mu}m$ by conventional sintering process. A relative density of ${\approx}96%$ with average grain size $7.3{\mu}m$ was obtained when the powder compacts were sintered at $850^{\circ}C$ even for a shorter duration of 10 min. In contrast, densification barely occurred at $800^{\circ}C$ for up to 12 h rather the microstruce showed the growth of abnormal grains. The grain growth behavior at different temperatures is discussed in terms of nonlinear growth rates with respect to the driving force. The sample sintered at $850^{\circ}C$ for 12 h showed enhanced electrical properties with leakage current density of $4{\times}10^{-7}A/cm^2$ at 1 kV/cm, remnant polarization $2P_r$ of $8{\mu}C/cm^2$ at 20 kV/cm, and minimal dissipation factor (tan ${\delta}$) of ~0.025 at $10^6$ Hz. These values are comparable to the previously reported values obtained using unconventional sintering techniques such as spark plasma sintering and rapid liquid phase sintering.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.11 no.12
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• pp.1122-1127
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• 1998

Group II-AF_2$films such as $CaF_2$, $SrF_2$, and $BaF_2$ have been commonly used many practical applications such as silicon on insulatro(SOI), three-dimensional integrated circuits, buffer layers, and gate dielectrics in filed effect transistor. This paper presents electrical and structural properties of fluoride films as a gate dielectric layer. Conventional gate dielectric materials of TFTs like oxide group exhibited problems on high interface trap charge density($D_it$), and interface state incorporation with O-H bond created by mobile hydrogen and oxygen atoms. To overcome such problems in conventional gate insulators, we have investigated $CaF_2$ films on Si substrates. Fluoride films were deposited using a high vacuum evaporation method on the Si and glass substrate. $CaF_2$ films were preferentially grown in (200) plane direction at room temperature. We were able to achieve a minimum lattice mismatch of 0.74% between Si and $CaF_2$ films. Average roughness of $CaF_2$ films was decreased from 54.1 ${\AA}$ to 8.40 ${\AA}$ as temperature increased form RT and $300^{\circ}C$. Well fabricated MIM device showed breakdown electric field of 1.27 MV/cm and low leakage current of $10^{-10}$ A/$cm^2$. Interface trap charge density between $CaF_2$ film and Si substrate was as low as $1.8{\times}10^{11}cm^{-2}eV^{-1}$.

• Korean Journal of Materials Research
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• v.13 no.10
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• pp.645-650
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• 2003

The microstructure and electrical characteristics of $Pr_{6}$ $O_{11}$ -based ZnO varistor ceramics composed of $ZnO-Pr_{6}$ $O_{ 11}$/$-CoO-Cr_2$$O_3$-$Dy_2$$O_3$-based ceramics were investigated with $Dy_2$$O_3$content in the range of 0.0∼2.0 mol%. As $Dy_2$$O_3$content was increased, the average grain size was decreased in the range of 18.6∼4.7 $\mu\textrm{m}$ and the density of the ceramic was decreased in the range of 5.53∼4.34 g/㎤. While, the varistor voltage was increased in the range of 39.4∼436.6 V/mm and the nonlinear exponent was in the range of 4.5∼66.6 with increasing $Dy_2$$O_3$content. The addition of $Dy_2$$O_3$highly enhanced the nonlinear properties of varistors, compared with the varistor without $Dy_2$$O_3$. In particular, the varistor with $Dy_2$$O_3$ content of 0.5 mol% exhibited the highest nonlinearity, in which the nonlinear exponent is 66.6 and the leakage current is 1.2 $\mu\textrm{A}$. The donor concentration and the density of interface states were decreased in the range of $(4.19∼0.33) ${\times}$10^{18}$ //㎤ and $(5.38∼1.74) ${\times}$10^{12}$ $\textrm{cm}^2$, respectively, with increasing $Dy_2$$O_3$content. The minimum dissipation factor of 0.0302 was obtained from 0.5mol% $Dy_2$$O_3$.

• Korean Journal of Materials Research
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• v.31 no.10
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• pp.539-545
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• 2021

The effect of Sm₂O₃ doping on the microstructure and electrical properties of the ZPCCA-based varistors is comprehensively investigated. The increase of doping content of Sm₂O₃ results in better densification (from 5.70 to 5.82 g/cm³) and smaller mean grain size (from 7.8 to 4.1 ㎛). The breakdown electric field increases significantly from 2568 to 6800 V/cm as the doping content of Sm₂O₃ increases. The doping of Sm₂O₃ remarkably improves the nonlinear properties (increasing from 23.9 to 91 in the nonlinear coefficient and decreasing from 35.2 to 0.2 µA/cm² in the leakage current density). Meanwhile, the doping of Sm₂O₃ reduces the donor concentration (the range of 2.73 × 10¹⁸ to 1.18 × 10¹⁸ cm^-3) of bulk grain and increases the barrier height (the range of 1.10 to 1.49 eV) at the grain boundary. The density of the interface states decreases in the range of of 5.31 × 10¹² to 4.08 × 10¹² cm^-2 with the increase of doping content of Sm₂O₃. The dielectric constant decreases from 1594.8 to 507.5 with the increase of doping content of Sm₂O₃.

• Current Photovoltaic Research
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• v.2 no.1
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• pp.8-13
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• 2014

ZnSe/$Zn_3P_2$ heterojunctions with a substrate configuration were fabricated using a series of cost-effective processes. Thin films of ZnTe and $Zn_3P_2$ were successively grown by close-spaced sublimation onto Mo-coated glass substrates. ZnSe layers thinner than 100nm were formed by annealing the $Zn_3P_2$ films in selenium vapor. Surface selenization generated a high density of micro-cracks which, along with voids, provided shunt paths and severely deteriorated the diode characteristics. Annealing the $Zn_3P_2$ film at $300^{\circ}C$ in a $ZnCl_2$ atmosphere before surface selenization produced a dense microstructure and prevented micro-crack generation. The mechanism of micro-crack generation by the selenization was described and the suppression effect of $ZnCl_2$ treatment on the micro-crack generation was explained. ZnSe/$Zn_3P_2$ heterojunctions with low leakage current ($J_0$ < $1{\mu}A/cm^2$) were obtained using an optimized surface selenization process with $ZnCl_2$ treatment. However, the series resistance was very high due to the presence of an electrical barrier between the ZnTe and $Zn_3P_2$ layers.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.12
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• pp.1724-1729
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• 2015

Chlorosulfonated polyethylene (CSPE) was not flooded seawater and flooded seawater & freshwater for 5 days, respectively, and these samples are referred to as BSF(before seawater flooding) and ASFF(after seawater & freshwater flooding), respectively. The apparent density, dissipation factor, relative permittivity, melting temperature, dielectric breakdown time and increased time of applied voltage are higher than those of BSF, but the insulating resistance, dielectric strength, percent elongation and glass transition temperature of ASFF are lower than those of BSF. The differential temperature of those is $0.026{\sim}0.028(^{\circ}C)$ after AC and DC voltage is applied to ASFF, respectively, and the differential temperature of those is $0.013{\sim}0.037(^{\circ}C)$ after AC and DC voltage is applied to BSF, respectively. In the case AC and DC voltage is applied to ASFF as well as BSF, the variations in temperature of AC voltage are higher than those of DC voltage. It is investigated that dielectric loss due to dissipation factor ($tan{\delta}$) is related to electric dipole conduction current. It is certain that the ionic (electron or hole) leakage current was increased by conducting ions such as $Na^+$, $Cl^-$, $Mg^{2+}$, $SO_4^{2-}$, $Ca^{2+}$ and $K^+$, those are related to cured atoms of O and S that relatively increased after seawater flooding.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.11
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• pp.70-77
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• 1998

Ni/SiC Schottky diodes have been fabricated using epitaxial 4H-SiC and 6H-SiC wafers. The epitaxial n-type layers were grown on $n^{+}$ substrates, with a doping density of 4.0$\times$10$^{16}$ c $m^{-3}$ and a thickness of 10${\mu}{\textrm}{m}$. Oxide-termination has been adopted in order to obtain high breakdown voltage and low leakage current. The fabricated Ni/4H-SiC and Ni/6H-SiC Schottky barrier diodes show excellent rectifying characteristics up to the measured temperature range of 55$0^{\circ}C$. In case of oxide-terminated Schottky barrier diodes, breakdown voltage of 973V(Ni/4H-SiC) and 920V(Ni/6H-SiC), and a very low leakage current of less than 1nA at -800V has been observed at room temperature. On non-terminated Schottky barrier diodes, breakdown voltages were 430V(Ni/4H-SiC) and 160v(Ni/6H-SiC). At room temperature, SBH(Schottky Barrier Height), ideality factor and specific on-resistance were 1.55eV, 1.3, 3.6$\times$10$^{-2}$ $\Omega$.$\textrm{cm}^2$ for Ni/4H-SiC Schottky barrier diodes, and 1.24eV, 1.2, 2.6$\times$10$^{-2}$$\Omega$.$\textrm{cm}^2$/ for Ni/SH-SiC Schottky barrier diodes, respectively. These results show that both Ni/4H-SiC and Ni/6H-SiC Schottky barrier diodes are very promising for high-temperature and high power applications.s..

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.114-119
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• 2004

Silicon Nitride thin films were deposited on p-type Si (100) substrates by atomic layer deposition (ALD) method at $550^{\circ}C$ using alternating exposures of $SiH_2Cl_2$ and $NH_3$, and the physical and electrical propeties of the deposited films were characterized. The thickness of the films was linearly increased with the number of deposition cycles, and the growth rate of the films was 0.13 nm/cycle with the reactant exposures of $3.0\times10^{9}$ L. The silicon nitride thin films deposited by Alf exhibited similar physical properties with the silicon nitride thin films deposited by low-pressure chemical vapor deposition (LPCVD) method in terms of refractive index and wet etch rate, lowering deposition temperature by more than 200 $^{\circ}C$. The ALD films showed the leakage current density of 0.79 nA/$\textrm{cm}^2$ at 3 MV/cm, which is lower than 6.95 nA/$\textrm{cm}^2$ of the LPCVD films under the same condition.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.