• 반도체디스플레이기술학회지
• /
• 제19권4호
• /
• pp.84-87
• /
• 2020

The properties of ultra-thin two-dimensional (2D) organic ferroelectric Langmuir-Blodgett (LB) films of the poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] were investigated to find possible applicability in flexible and wearable electronics applications. In the C-V characteristics of the MFM capacitor of 2-monolayer of 5 nm films, a butterfly hysteresis curve due to the ferroelectricity of P(VDF-TrFE) was confirmed. Typical residual polarization value was measured at 2μC/㎠. When the MFM capacitor with ultra-thin ferroelectric film was measured by applying a 10 Hz bipolar pulse, it was shown that 65% of the initial polarization value in 105 cycles deteriorated the polarization. The leakage current density of the 2-monolayer film was maintained at about 5 × 10-8 A/㎠ for the case at a 5MV/cm electric field. The resistivity of the 2-monolayer film in the case at an electric field at 5 MV/cm was more than 2.35 × 1013 Ω·cm.

• Nuclear Engineering and Technology
• /
• 제54권12호
• /
• pp.4693-4697
• /
• 2022

Parylene coating was adopted on CdZnTe (CZT) detector as a mechanical protection layer after wet passivation with hydrogen peroxide (H₂O₂) and ammonium fluoride (NH₄F). Wet chemical passivant lose their effectiveness when exposed to the ambient conditions for a long time. Parylene coating could protect the effectiveness of passivation, by mechanically blocking the exposure to the ambient conditions. Stability of CZT detector was tested with the measurement of leakage current density and response to radio-isotopes. When the enough thickness of parylene (>100 ㎛) is adopted, parylene is a promising protection layer thereby ensuring the performance and long-term stability of CZT detectors.

• 한국전자통신학회논문지
• /
• 제17권6호
• /
• pp.1175-1180
• /
• 2022

STI는 반도체 소자의 소형화 및 고집적화에 따른 광역 평탄화를 위한 공정 기술로써 많은 연구가 이루어져 왔다. 본 연구에서는 STI의 profile 개선을 위한 방법으로 STI 건식각 후 HF 용액에 의한 pad oxide 습식각과 O₂+CF₄ 건식각을 제안하였다. 이 공정 기술은 기존의 방법보다 소자의 밀집도에 따른 패턴간의 프로파일 불균형과 누설전류의 개선을 나타내었다. 또한 동일한 STI 깊이와 HLD 증착를 갖는 디바이스에 대하여 CMP 후 HLD 두께를 측정한 결과 디바이스 밀도에 따라 측정값이 다르게 나타났고 이는 CMP 후 디바이스 밀도에 따른 질화막의 두께 차이 및 슬러리의 선택비에 기인됨을 확인하였다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2002년도 하계학술대회 논문집 B
• /
• pp.923-925
• /
• 2002

The existing contactless inductive coupler has many problems because of its large volume and high level of exciting current, so a new contactless inductive coupler is being required under the circumstances and the load requirement. For a contactless inductive coupler in the manufacturing equipment of semiconductor, the coupler's efficiency is low because of its small magnetic inductance and large leakage inductance. Moreover, the high frequency switching to increase energy density per unit volume increases the iron loss and the eddy current loss, so it must be considered deeply when selecting core materials. Therefore, this paper presents core materials and shape to improve the performance of the contactless inductive coupler according to the coil positions.

• 한국재료학회지
• /
• 제14권8호
• /
• pp.542-546
• /
• 2004

We report a new fabrication process for high performance triode type CNT field emitters and their superior electrical properties. The CNT-based triode-type field emitter structure was fabricated by the conventional semiconductor processes. The keys of the fabrication process are spin-on-glass coating and trim-and-leveling of the carbon nanotubes grown in trench structures by employing a chemical mechanical polishing process. They lead to strong adhesion and a uniform distance from the carbon nanotube tips to the electrode. The measured emission property of the arrays showed a remarkably uniform and high current density. The gate leakage current could be remarkably reduced by coating of thin $SiO_{2}$ insulating layer over the gate metal. The field enhancement factor(${\beta}$) and emission area(${\alpha}$) were calculated from the F-N plot. This process can be applicable to fabrication of high power CNT vacuum transistors with good electrical performance.

• 한국재료학회:학술대회논문집
• /
• 한국재료학회 2009년도 추계학술발표대회
• /
• pp.48.1-48.1
• /
• 2009

Performance of organic field-effect transistors (OFETs) with various temperature-cured polyacrylate(PA) copolymer as a gate insulator was studied. The PA thin film, which was cured at an optimized temperature, showed high dielectric strength (>7 MV/cm), low leakage current density ($5{\times}10^{-9}\;A/cm^2$ at 1 MV/cm) and enabled negligible hysteresis in MIS capacitor and OFET. A field-effect mobility of ${\sim}0.6\;cm^2/V\;s$, on/off current ratio (Ion/Ioff) of ${\sim}10^5$ and inverse subthreshold slope (SS) as low as 1.22 V/decwere achieved. The high dielectric strength made it possible to scale down the thickness of dielectric, and low-voltage operation of -5 V was successfully realized. The chemical changes were monitored by FT-IR. The morphology and microstructure of the pentacene layer grown on PA dielectrics were also investigated and correlated with OFET device performance.

• 대한전기학회논문지:전기물성ㆍ응용부문C
• /
• 제52권4호
• /
• pp.159-163
• /
• 2003

ln this work, we studied electrical characteristics and leakage current mechanism of $Ta_2O_{5}$ MOS(Metal-Oxide-Semiconductor) devices. $Ta_2O_{5}$ thin film (63 nm) was deposited by ALD(Atomic Layer Deposition) method at temperature of 235 $^{\circ}C$. The structures of the $Ta_2O_{5}$ thin films were examined by XRD(X-Ray Diffraction). From XRD, it is found that the structure of $Ta_2O_{5}$ is single phase and orthorhombic. From capacitance-voltage (C-V) anaysis, the dielectric constant was 19.4. The temperature dependence of current density-electric field (J-E) characteristics of $Ta_2O_{5}$ thin film was studied at temperature range of 300 - 423 K. In ohmic region (<0.5 MV/cm), the resistivity was 2.456${\times}10^{14}$ ($\omega{\cdot}cm$ at 348 K. The Schottky emission is dominant at lower temperature range from 300 to 323 K and Poole-Frenkel emission is dominant at higher temperature range from 348 to 423 K.

• 한국세라믹학회지
• /
• 제35권9호
• /
• pp.945-952
• /
• 1998

Ferroelectric Sr0.8Bi2.4Ta2O9 stock solutions were prepared by MOD(Metaloganic Decompostion) process. The phase transformation for the layered perovskite of the SBT thin films by changing RTA(Rapid her-mal Annealing) temperatuer from 700$^{\circ}C$to 780$^{\circ}C$ were observed using XRD and SEM. Layered perovskite phase began to appear above 740$^{\circ}C$ and then SBT thin films were annealed at 800$^{\circ}C$ for 1hr for its com-plete crystallization. The specimens showed well shaped hysteresis curves without post annealing that car-ried out after deposition of Pt top electrode. The SBT thin films showed the asymmetric ferroelectric pro-perties. It was confirmed that the properties were caused by interface effect to SBT and electrode by leak-age current density measurement and asymmetric properties reduced by post annealing. At post annealing temperature of 800$^{\circ}C$ remanant polarization values (2Pr) were 6.7 9 ${\mu}$C/cm2 and those of leakage current densities were 3.73${\times}$10-7 1.32${\times}$10-6 A/cm2 at 3, 5V respectively. Also bismuth bonding types of SBT thin film surface were observed by XPS.

• Transactions on Electrical and Electronic Materials
• /
• 제11권3호
• /
• pp.93-105
• /
• 2010

Complementary metal-oxide-semiconductor (CMOS) technology scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past three decades. However, as the technology scaling enters nanometer regime, CMOS devices are facing many serious problems such as increased leakage currents, difficulty on increase of on-current, large parameter variations, low reliability and yield, increase in manufacturing cost, and etc. To sustain the historical improvements, various innovations in CMOS materials and device structures have been researched and introduced. In parallel with those researches, various new nanoelectronic devices, so called "Beyond CMOS Devices," are actively being investigated and researched to supplement or possibly replace ultimately scaled conventional CMOS devices. While those nanoelectronic devices offer ultra-high density system integration, they are still in a premature stage having many critical issues such as high variations and deteriorated reliability. The practical realization of those promising technologies requires extensive researches from device to system architecture level. In this paper, the current researches and challenges on nanoelectronics are reviewed and critical tasks are summarized from device level to circuit design/CAD domain to better prepare for the forthcoming technologies.

• ETRI Journal
• /
• 제39권1호
• /
• pp.62-68
• /
• 2017

In this paper, we present the design and characterization analysis of a cascode GaN field-effect transistor (FET) for switching power conversion systems. To enable normally-off operation, a cascode GaN FET employs a low breakdown voltage (BV) enhancement-mode Si metal-oxide-semiconductor FET and a high-BV depletion-mode (D-mode) GaN FET. This paper demonstrates a normally-on D-mode GaN FET with high power density and high switching frequency, and presents a theoretical analysis of a hybrid cascode GaN FET design. A TO-254 packaged FET provides a drain current of 6.04 A at a drain voltage of 2 V, a BV of 520 V at a drain leakage current of $250{\mu}A$, and an on-resistance of $331m{\Omega}$. Finally, a boost converter is used to evaluate the performance of the cascode GaN FET in power conversion applications.