• Title/Summary/Keyword: Leakage Reduction

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Reduction of Power Consumption for Constant Pressure Control of Variable Swash Plate-type Piston Pump by Varying the Pump Speed (가변 용적형 사판식 피스톤 펌프의 회전 속도 조절에 의한 정압 제어 소비 동력 절감)

  • Kim, J.H.;Hong, Y.S.
    • Journal of Drive and Control
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    • v.11 no.4
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    • pp.53-60
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    • 2014
  • This paper proposes a control scheme to reduce the power consumption of a variable displacement swash-plate type piston pump supplying oil to a valve-controlled hydraulic cylinder at constant pressure. Whenever flow rate demand was absent, the swash plate angle and the pump speed were changed to the minimum values required to compensate for the internal leakage flow. In response to command signals, the pump speed was changed in proportion to the absolute mean value of the speed component for position commands. At the same time, a pressure regulator was activated to maintain constant system pressure by precisely adjusting the pump speed with the swash plate angle fixed at the maximum. The conventional system consisting of a pressure-compensated variable displacement type pump is driven at a constant speed of 1,800rpm. By comparison, computer simulation and experimental results showed that idling power at stand-by status could be reduced by up to 70% by reducing the pump speed from 1,800rpm to 300rpm and the swash plate angle to the minimum.

Performance Improvement of a Swash Plate Type Piston Pump in the Low-Speed Range by a DLC Coating (DLC 코팅에 의한 사판식 피스톤 펌프의 저속 영역 동력 손실 개선)

  • Hong, Y.S.;Kim, J.H.;Lee, S.L.
    • Journal of Drive and Control
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    • v.11 no.4
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    • pp.25-31
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    • 2014
  • This paper details application of a DLC(Diamond Like Carbon)-coating to the swash plate and the ball joint of pistons that make sliding contact with the piston shoes of an axial piston pump. This process, aimed to reduce the frictional and leakage power losses of the hydrostatic piston shoe bearings at the low speed range. At lower speeds than 100rpm, the positive effects of the DLC-coating on the power loss reduction of the hydrostatic piston shoe bearings could be confirmed. These effects resulted in little improvement in volumetric efficiency of the test pump, but the mechanical efficiency could be raised by up to 5% at 100rpm; here, the DLC-coated swash plate played a more dominant role than the DLC-coated ball joint.

A Study on the Optimal Installation Technology of LPG Storage Tank through Taguchi Method (다구찌 기법을 통한 LPG 저장탱크시공방법의 최적화에 관한 연구)

  • Leem, Sa-Hwan;Huh, Yong-Jeong;Paek, Seung-Cheol;Lee, Jong-Rark
    • Journal of the Korean Society of Safety
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    • v.25 no.6
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    • pp.98-102
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    • 2010
  • LPG (Liquefied Petroleum Gas) vehicles in metropolitan area are being applied to improve air quality and have been proven effective for the reduction of air pollutant. In addition, the demand of gas as an eco-friendly energy source has being increased. With the LPG filling station is also increasing every year. These gas stations are required to install the securest storage tank because of possibility of causing huge loss of life and property. Therefore, in this paper, underground containment type is proposed as installation of the LPG storage tank using Taguchi method, which is considered to be more safe, economical, efficient, easy checking and simple construction method than any other. If leakage, economics, real estate utilization rate, safety, easy to check, simple construct about above ground, buried underground and underground containment storage tank are analyzed by Taguchi method, real estate utilization rate, economic and safety in turn are improved. Therefore, the underground containment storage tank is a optimal installation technology.

Beamforming Optimization for Multiuser Two-Tier Networks

  • Jeong, Young-Min;Quek, Tony Q.S.;Shin, Hyun-Dong
    • Journal of Communications and Networks
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    • v.13 no.4
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    • pp.327-338
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    • 2011
  • With the incitation to reduce power consumption and the aggressive reuse of spectral resources, there is an inevitable trend towards the deployment of small-cell networks by decomposing a traditional single-tier network into a multi-tier network with very high throughput per network area. However, this cell size reduction increases the complexity of network operation and the severity of cross-tier interference. In this paper, we consider a downlink two-tier network comprising of a multiple-antenna macrocell base station and a single femtocell access point, each serving multiples users with a single antenna. In this scenario, we treat the following beamforming optimization problems: i) Total transmit power minimization problem; ii) mean-square error balancing problem; and iii) interference power minimization problem. In the presence of perfect channel state information (CSI), we formulate the optimization algorithms in a centralized manner and determine the optimal beamformers using standard convex optimization techniques. In addition, we propose semi-decentralized algorithms to overcome the drawback of centralized design by introducing the signal-to-leakage plus noise ratio criteria. Taking into account imperfect CSI for both centralized and semi-decentralized approaches, we also propose robust algorithms tailored by the worst-case design to mitigate the effect of channel uncertainty. Finally, numerical results are presented to validate our proposed algorithms.

Fabrication and Device Performance of Tera Bit Level Nano-scaled SONOS Flash Memories (테라비트급 나노 스케일 SONOS 플래시 메모리 제작 및 소자 특성 평가)

  • Kim, Joo-Yeon;Kim, Moon-Kyung;Kim, Byung-Cheul;Kim, Jung-Woo;Seo, Kwang-Yell
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.20 no.12
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    • pp.1017-1021
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    • 2007
  • To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

A Study on Application for Deck Plate Substitute Type Wood System Form of Frame Type Parking Lot (골조형 주차장의 Deck Plate 대체형 목제 시스템 거푸집 적용성 연구)

  • Shin, Yong-Jae;Shin, Woon-Sik;Heo, Jae-Won;Lim, Nam-Gi
    • Proceedings of the Korean Institute of Building Construction Conference
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    • 2006.11a
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    • pp.123-126
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    • 2006
  • Existing Deck Plate for a one of system forms, there is various advantage and application actual results increasing rapidly. But design of deck is depending on engineering data collections or design data on deck manufacture ordinarily. When construct, is responsible for deflection occurrence, And Because confirmation of crack occurrence region is impossible, there is difficulty of repair, reinforcement about crack and water leakage. According to got following conclusion as result that economic performance, preservation administration and repair reinforcement develops easy using steel truss snap tie by wedge pin on coating plywood that is slab Panel Wood System Form method of construction there is Deck Plate's advantage. (1) In stab lower part is exposed disjointing in which a criminal is fastened to be interrogated after construction acceptance and repair, reinforcement of crack is possible (2) Construction cost curtailment effect of about 29.2% than conventional type and about 10% than deck plate (3) Construction period reduction of about 3 day than conventional type and about 0.3 day than deck plate (4) Labor curtailment effect more than about $29{\sim}50%$ from conventional type

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Research of Corrosion Growth Degree According in Liquid Environment of Waterworks and Sewer Piping Material (상·하수 배관재의 수 환경에서 부식진전도 연구)

  • Park, Kyeong-Dong;Ki, Woo-Tae;Yu, Hyeong-Ju;Kim, Dong-Uk
    • Journal of the Korean Society of Manufacturing Process Engineers
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    • v.5 no.4
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    • pp.33-40
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    • 2006
  • The quality of the supply water which is supplied to consumer is not the thing of water after filtrating but the thing of water from faucet through pipe. As a result, heavy metals and microorganism, that is the major materials, which cause the distrust of the supply water is generated by supply process. Especially, the heavy metal is generated by the corrosion of waterworks. Besides, rupture by corrosion of pipe becomes the factor of supply water's pollution in waterworks and the factor of pollution of the soil and environment in drain pipe. Therefore, this research examined the weight reduction electric potential measure to measure the corrosion degree of piping materials after testing the corrosion of piping materials(Copper Pipe, Galvanized Steel Pipe, Stainless Steel Pipe) which is generally used at the moment in various corrosion environments(subterranean water, supply water, 3.5% NaCl, 3.5% $HNO_3$). And let me show basic design data about problem occurrence such as leakage water, rust water, inside and outside corrosion from this.

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Ion beam etching of sub-30nm scale Magnetic Tunnel Junction for minimizing sidewall leakage path

  • Kim, Dae-Hong;Kim, Bong-Ho;Chun, Sung-Woo;Kwon, Ji-Hun;Choi, Seon-Jun;Lee, Seung-Beck
    • Proceedings of the Korean Magnestics Society Conference
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    • 2011.12a
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    • pp.29-30
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    • 2011
  • We have demonstrated the fabrication of sub 30 nm MTJ pillars with PMA characteristics. The multi-step IBE process performed at $45^{\circ}$ and $30^{\circ}$, using NER resulted in almost vertical side profiles. There deposition on the sidewalls of the NER prevented lateral etching of the resist hard mask allowing vertical MTJ side profile formation without any reduction in the lithographically defined resist lateral dimensions. For the 28nm STT-MTJ pillars, the measured TMR ratio was 13 % with resistance of 1 $k{\Omega}$, which was due to remaining redeposition layers less than 0.1 nm thick. With further optimization in multi-step IBE conditions, it will be possible to fabricate fully operating sub 30 nm perpendicular STT-MTJ structures for application to future non-volatile memories.

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Dual-Output Single-Stage Bridgeless SEPIC with Power Factor Correction

  • Shen, Chih-Lung;Yang, Shih-Hsueh
    • Journal of Power Electronics
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    • v.15 no.2
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    • pp.309-318
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    • 2015
  • This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current-direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an $85-265V_{rms}$ universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.

Schottky barrier poly-Si thin film transistor by using erbium-silicided source and drain (어븀-실리사이드를 이용한 쇼트키 장벽 다결정 실리콘 박막 트랜지스터)

  • Shin, Jin-Wook;Koo, Hyun-Mo;Jung, Myung-Ho;Choi, Chel-Jong;Jung, Won-Jin;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.11a
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    • pp.75-76
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    • 2007
  • Poly-Si Schottky barrier Thin Film Transistor (SB-TFT) is manufactured with erbium silicided source/drain. High quality poly-Si film was obtained by crystallizing the amorphous Si film with Excimer laser annealing (ELA) method. The fabricated poly-Si SB-TFT devices showed low leakage current and large on/off current ratio. Moreover, the electrical characteristics were considerably improved by 3% $H_2/N_2$ gas annealing, which is attributed to the reduction of trap states at the grain boundaries and interface trap states at gate oxide/poly-si channel.

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