Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Fabrication and Device Performance of Tera Bit Level Nano-scaled SONOS Flash Memories

테라비트급 나노 스케일 SONOS 플래시 메모리 제작 및 소자 특성 평가

  • 김주연 (울산과학대학 전기전자학부 반도체응용) ;
  • 김문경 ;
  • 김병철 (진주산업대학 전자공학부) ;
  • 김정우 (삼성전자 메모리 사업부 반도체 R&D center) ;
  • 서광열 (광운대학교 전자재료공학과)
  • Published : 2007.12.01
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Abstract

To implement tera bit level non-volatile memories of low power and fast operation, proving statistical reproductivity and satisfying reliabilities at the nano-scale are a key challenge. We fabricate the charge trapping nano scaled SONOS unit memories and 64 bit flash arrays and evaluate reliability and performance of them. In case of the dielectric stack thickness of 4.5 /9.3 /6.5 nm with the channel width and length of 34 nm and 31nm respectively, the device has about 3.5 V threshold voltage shift with write voltage of $10\;{\mu}s$, 15 V and erase voltage of 10 ms, -15 V. And retention and endurance characteristics are above 10 years and $10^5$ cycle, respectively. The device with LDD(Lightly Doped Drain) process shows reduction of short channel effect and GIDL(Gate Induced Drain Leakage) current. Moreover we investigate three different types of flash memory arrays.

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References

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  1. The Characteristics of p-channel SONOS Transistor for the NAND Charge-trap Flash Memory vol.22, pp.1, 2009, https://doi.org/10.4313/JKEM.2009.22.1.007