• The Transactions of the Korean Institute of Electrical Engineers P
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• v.60 no.3
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• pp.126-132
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• 2011

A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.

• Journal of IKEEE
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• v.23 no.2
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• pp.722-726
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• 2019

In this paper, we propose a low drop-out (LDO) regulator with improved power-supply rejection (PSR) characteristics in the high frequency region. In particular, an NMOS transistor with a high output resistance is added as a compensation circuit to offset the high frequency noise passing through the finite output resistance of the PMOS power switch. The elimination of power supply noise by the compensating transistor was explained analytically and presented as the direction for further improvement. The circuit was fabricated in a $0.35-{\mu}m$ standard CMOS process and Specter simulations were carried out to confirm the PSR improvement of 26 dB compared to the conventional LDO regulator at 10 MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.10
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• pp.239-244
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• 2013

This paper presents a design of the CMOS LDO regulator with a UVLO protection function for a high speed PMIC. Proposed LDO regulator circuit consists of a BGR reference circuit, an error amplifier and a power transistor and so on. UVLO block between the power transistor and the power supply is added for a low input protection function. Also, UVLO block showed normal operation with turn-off voltage of 2.7V and turn-on voltage of 4 V in condition of 5 V power supply. Proposed circuit generated fixed 3.3 V from a supply of 5V. From SPICE simulation results using a $1{\mu}m$ high voltage CMOS technology, simulation results were 5.88 mV/V line regulation and 27.5 uV/mA load regulation with load current 0 mA to 200 mA.

• ETRI Journal
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• v.42 no.5
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• pp.790-798
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• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.

• Journal of IKEEE
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• v.19 no.3
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• pp.304-310
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• 2015

A SCALDO(Supercapacitor Assisted LDO) regulator is a new regulator having advantages of a SMPS(Switch Mode Power Supply) which has a good efficiency and a LDO(Low Drop-out) regulator which has stable output characteristics and good EMI(Electro Magnetic Interference) characteristics. However, a conventional SCALDO regulator needs a lot of power consumption to control its switches and it drops an efficiency of the circuit. In this paper, to reduce switching power consumption and improve an efficiency of the circuit, a new SCALDO regulator adopting MOSFETs as its switching parts is proposed and it is found out that the proposed SCALDO regulator has the maximum 9.5% higher efficiency than the conventional SCALDO regulator. We also try to simplify production process of the circuit by changing switching control method of the circuit from MCU(Micro-controller unit) based firmware control to hardware control using a comparator and a T-F/F(Flip Flop).

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.3
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• pp.152-157
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• 2015

Various power supply noise sources in a system integrated circuit degrade the performance of a low dropout (LDO) regulator. In this paper, a capacitor-less low dropout regulator for enhanced power supply rejection is proposed to provide good power supply rejection (PSR) performance. The proposed scheme is implemented by an additional capacitor at a gate node of a pass transistor. Simulation results show that the PSR performance of the proposed LDO regulator depends on the capacitance value at the gate node of the pass transistor, that it can be maximized, and that it outperforms a conventional LDO regulator.

• ETRI Journal
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• v.37 no.5
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• pp.961-971
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• 2015

This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a$0.11{\mu}m$ CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at $20{\mu}A$ to $200{\mu}A$ load current.

• 전자공학회논문지 IE
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• v.48 no.4
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• pp.13-18
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• 2011

In this paper, we have examined electrical characteristics of LDO regulator according to the process variation using a 1 ${\mu}m$ 20 V high voltage CMOS process. The electrical analysis of LDO regulator have been performed with three kind of SPICE parameter sets (Typ : typical, FF : fast, SS : slow) by process variation which cause change of SPICE parameter such as threshold voltage and effective channel length of MOS devices. From simulation results, we confirmed that in case of SS type SPICE parameter set, the LDO regulator has 3.6 mV/V line regulation, 0.4 mV/mA load regulation and 0.86 ${\mu}s$ output voltage settling time. And in case of Typ type SPICE parameter set, the LDO regulatorhas 4.2 mV/V line regulation, 0.44 mV/mA load regulation and 0.62 ${\mu}s$ output voltage settling time. Finally, in the FF type SPICE parameter set, the LDO regulator has 7.0 mV/V line regulation, 0.56 mV/mA load regulation and 0.27 ${\mu}s$ output voltage settling time.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.4
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• pp.1222-1228
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• 2010

This paper presents a design of the CMOS LDO regulator with a fast transient response for a high speed PMIC(power management integrated circuit). Proposed LDO regulator circuit consists of a reference voltage circuit, an error amplifier and a power transistor. 2-stage wide-band OTA buffer between error amplifier and power transistor is added for a good output stability. Although conventional source follower buffer structure is simple, it has a narrow output swing and a low S/N ratio. In this paper, we use a 2-stage wide-band OTA instead of source follower structure for a buffer. From HSPICE simulation results using a $0.5{\mu}m$ CMOS standard technology, simulation results were 16 mV/V line regulation and 0.007 %/mA load regulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.1
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• pp.71-80
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• 2015

LDO(Low Drop-Out) regulators have become an essential building block in modern PMIC(Power Managment IC) to extend battery life of electronic devices. In this paper, we optimize capacitor-less LDO regulator via Geometric Programming(GP) designed using Dongbu HiTek $0.5{\mu}m$ BCDMOS process. GP-compatible models for stability and PSR of LDO regulators are derived based on monomial formulation of transistor characteristics. Average errors between simulation and the proposed model are 9.3 % and 13.1 %, for phase margin and PSR, respectively. Based on the proposed models, the capacitor-less LDO optimization can be performed by changing the PSR constraint of the design. The GP-compatible performance models developed in this work enables the design automation of capacitor-less LDO regulator for different design target specification.