• Title/Summary/Keyword: KT/C noise

Search Result 7, Processing Time 0.02 seconds

A Design of a Reconfigurable 4th Order ΣΔ Modulator Using Two Op-amps (2개의 증폭기를 이용한 가변 구조 형의 4차 델타 시그마 변조기)

  • Yang, Su-Hun;Choi, Jeong-Hoon;Yoon, Kwang Sub
    • Journal of the Institute of Electronics and Information Engineers
    • /
    • v.52 no.5
    • /
    • pp.51-57
    • /
    • 2015
  • In this paper, in order to design the A / D converter with a high resolution of 14 bits or more for the biological signal processing, CMOS delta sigma modulator that is a 1.8V power supply voltage - were designed. we propose a new structure of The fourth order delta-sigma modulator that needs four op amps but we use only two op amps. By using a time -interleaving technique, we can re-construct the circuit and reuse the op amps. Also, we proposed a KT/C noise reduction circuit to reduce the thermal noise from a noisy resistor. We adjust the size of sampling capacitor between sampling time and integrating time, so we can reduce almost a half of KT/C noise. The measurement results of the chip is fabricated using a Magna 0.18um CMOS n-well1 poly 6 metal process. Power consumption is $828{\mu}W$ from a 1.8V supply voltage. The peak SNDR is measured as a 75.7dB and 81.3dB of DR at 1kHz input frequency and 256kHz sampling frequency. Measurement results show that KT/C noise reduction circuit enhance the 3dB of SNDR. FOM of the circuit is calculated to be 142dB and 41pJ / step.

A Reconfigurable 4th Order ΣΔ Modulator with a KT/C Noise Reduction Circuit

  • Yang, Su-Hun;Seong, Jae-Hyeon;Yoon, Kwang-Sub
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.17 no.2
    • /
    • pp.294-301
    • /
    • 2017
  • This paper presents a low power ${\Sigma}{\Delta}$ modulator for an implantable chip to acquire a bio-signal such as EEG, DBS, and EMG. In order to reduce a power consumption of the proposed fourth order modulator, two op-amps utilized for the first two integrators are reconfigured to drive the second two integrators. The KT/C noise reduction circuit in the first two integrators is employed to enhance SNR of the modulator. The proposed circuit was fabricated in a 0.18 um CMOS n-well 1 poly 6 metal process with the active chip core area of $900um{\times}800um$ and the power consumption of 830 uW. Measurement results were demonstrated to be SNDR of 76 dB, DR of 77 dB, ENOB of 12.3 bit at the input frequency of 250 Hz and the clock frequency of 256 kHz. FOM1 and FOM2 were measured to be 41 pJ/step and 142.4 dB, respectively.

A Study on the Cutting and Vibration Characteristic of Ultrasonic Vibration Cutting (초음파 진동선삭에서의 절삭 및 진동특성에 관한 연구)

  • 이규배;임영호;이계철
    • Journal of KSNVE
    • /
    • v.4 no.2
    • /
    • pp.147-154
    • /
    • 1994
  • In this study, ultransonic vibration cutting system was contructed by installing throw-away-tool tip (KT 350) by screw lock on the bending vibration mode in free-free beam. During the conventional cutting and ultransonic conventional cutting of SM45C, variations of cutting force, roughness and acceleration were measured. The results were compared and analyzed in detail, and it was found that the ultransonic vibration cutting was more effective in reducing cutting force compareed with the conventional cutting .

  • PDF

Design of 4th Order ΣΔ modulator employing a low power reconfigurable operational amplifier (전력절감용 재구성 연산증폭기를 사용한 4차 델타-시그마 변조기 설계)

  • Lee, Dong-Hyun;Yoon, Kwang-Sub
    • Journal of IKEEE
    • /
    • v.22 no.4
    • /
    • pp.1025-1030
    • /
    • 2018
  • The proposed modulator is designed by utilizing a conventional structure employing time division technique to realize the 4th order delta-sigma modulator using one op-amp. In order to reduce the influence of KT/C noise, the capacitance in the first and second integrators reused was chosen to be 20pF and capacitance of third and fourth integrators was designed to be 1pF. The stage variable technique in the low power reconfigurable op-amp was used to solve the stability issue due to different capacitance loads for the reduction of KT/C noise. This technique enabled the proposed modulator to reduce the power consumption of 15% with respect to the conventional one. The proposed modulator was fabricated with 0.18um CMOS N-well 1 poly 6 metal process and consumes 305uW at supply voltage of 1.8V. The measurement results demonstrated that SNDR, ENOB, DR, FoM(Walden), and FoM(Schreier) were 66.3 dB, 10.6 bits, 83 dB, 98 pJ/step, and 142.8 dB at the sampling frequency of 256kHz, oversampling ratio of 128, clock frequency of 1.024 MHz, and input frequency of 250 Hz, respectively.

A Study on the Induced Voltages on Subscriber Telecommunication Lines from High-Speed Electrified Railway Line (고속전철에 의한 통신선로 전력유도 현상에 관한 고찰)

  • Oh, Ho-Seok;Kang, Seong-Yong;Yun, Ju-Yeong;Kim, Hak-Chul;Choi, Kyung
    • Journal of the Institute of Electronics Engineers of Korea TC
    • /
    • v.45 no.10
    • /
    • pp.71-79
    • /
    • 2008
  • This paper analyzed the voltage induction phenomena on the telecommunication lines by electromagnetic coupling from high-speed A.C. electrified railway. The induced common mode voltages and the induced differential mode voltage on the telecommunication line was measured by notified standard method in the regulation of Korea. The test lines consist of 2 separated lines of 20 m and 300 m in influence distance each for comparison, with 2km inducing length. The analysis is made on the induced voltages from the different influence distances and the different earthing points, and also on the waveform and spectrum distributions. It is proved that the induction is arisen so good and the measured values are fair enough against noise such as the earth voltage differencing, and the current measuring scheme is also rightful.

Analysis of DIC Platform and Image Quality with FHD for Displacement Measurement (FHD급 DIC 플랫폼의 변위계측용 영상품질 분석)

  • Park, Jongbae;Kang, Mingoo
    • Journal of Internet Computing and Services
    • /
    • v.19 no.1
    • /
    • pp.105-111
    • /
    • 2018
  • This paper presents the analysis of image quality with FHD(Full HD) resolution camera equipped DIC(Digital Image Correlation) platform for the measurement of the architectural structure's relative displacement. DIC platform was designed based on i.MX6 of Freescale. Displacement measurement based on DIC method, the error is affected by image quality factors as pixel number, brightness, contrast, and SNR[dB](Signal to Noise Ratio). The effect were analyzed. The displacement of ROI(Region Of Interest) area within the image was measured by sub-pixel units based on DIC method. The non-contact telemetry property of DIC method, it can be used to long distance non-contact measurement. The various displacement results was measured and analyzed with the image quality factor adjustment according to the distance(25m, 35m, 50m).

Design of FPGA Camera Module with AVB based Multi-viewer for Bus-safety (AVB 기반의 버스안전용 멀티뷰어의 FPGA 카메라모듈 설계)

  • Kim, Dong-jin;Shin, Wan-soo;Park, Jong-bae;Kang, Min-goo
    • Journal of Internet Computing and Services
    • /
    • v.17 no.4
    • /
    • pp.11-17
    • /
    • 2016
  • In this paper, we proposed a multi-viewer system with multiple HD cameras based AVB(Audio Video Bridge) ethernet cable using IP networking, and FPGA(Xilinx Zynq 702) for bus safety systems. This AVB (IEEE802.1BA) system can be designed for the low latency based on FPGA, and transmit real-time with HD video and audio signals in a vehicle network. The proposed multi-viewer platform can multiplex H.264 video signals from 4 wide-angle HD cameras with existed ethernet 1Gbps. and 2-wire 100Mbps cables. The design of Zynq 702 based low latency to H.264 AVC CODEC was proposed for the minimization of time-delay in the HD video transmission of car area network, too. And the performance of PSNR(Peak Signal-to-noise-ratio) was analyzed with the reference model JM for encoding and decoding results in H.264 AVC CODEC. These PSNR values can be confirmed according the theoretical and HW result from the signal of H.264 AVC CODEC based on Zynq 702 the multi-viewer with multiple cameras. As a result, proposed AVB multi-viewer platform with multiple cameras can be used for the surveillance of audio and video around a bus for the safety due to the low latency of H.264 AVC CODEC design.