• Journal of Aerospace System Engineering
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• v.13 no.3
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• pp.40-47
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• 2019

This paper proposes the environment construction and test method of system integration laboratory (SIL) and system integration test (SIT) for verification of interface between onboard equipment and ground control equipment of unmanned aerial systems (UAS). This research also describes the interface environment between subsystems built in SIL and verification methods for the systems' operation logic through simulated flights. Similarly, the paper handles the ground integration test process of UAS in the real testing environments.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.291-294
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• 2002

This paper proposed interface test method for performance verification of communication and broadcasting satellite between communication and broadcasting satellite payload and EGSE(Electrical Ground Support Equipment). We need ground support equipment for test them to performance verification and conform interface function of payload. This paper define tile telemetry transfer method for control payload using GSE(Ground Support Equipment) and receive telemetry data collected from GSE through bus simulator

• Journal of the Korean Society for Railway
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• v.7 no.2
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• pp.114-119
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• 2004

According to the computerization of railway signalling systems. the communication protocol for interface between these systems are required. Therefore the new communication protocol for railway signaling system is required. Generally, there are two verification method for new designed protocol in the industrial and academic fields. One is the laboratory testing method which is very popular and general technique. In our research the comparison between existing and new designed protocol for signaling is described and the verification test results are also represented. From these laboratory test, we are verified the conformance of new designed protocol. Another method is verified by formal method. The format verification method is widely used at safety-critical system design but this approach is nor popular at verification communication protocol. However it is very important to verify the safety of new designed protocol for railway signaling system because signaling systems are very safety-critical systems. So, the methodology for formal verification of designed protocol is also reviews in this paper.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.4 s.310
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• pp.39-49
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• 2006

This paper proposes an efficient verification environment of PCI Express controller that is the future I/O interface. This verification environment consists of a test vector generator, a test bench, and two abstract memories. We also define the assembler set to generate the verification scenarios. In this paper, we propose the random test environment which consists of a random vector generator, a .simulator part, and a compare engine. This verification methodology is useful to find the special errors which are not detected by the basic-behavioral test and hardware-design test.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.544-547
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• 2007

Because data processing systems in recent years are more complicated, main function of the data processing is divided as several sub-functions which are implemented and verified in each subsystem of the data processing system. For the verification of data processing system, many interface tests among subsystems are required and also a lot of simulation systems are demanded. This paper proposes CTHS (Common Test Harness System) for satellite ground segment development which has all of functions for interface test of the data processing system in one PC. Main functions of the CTHS software are data interface, system log generation, and system information display. For the interface test of the data processing system, all of actions of the CTHS are executed by a pre-defined operation scenario which is written by purpose of the data processing system test.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.93-96
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• 2002

It is said that the verification effort occupies about 50-70 percent of the total effort of a System-On-A-Chip. This paper aims to develop a test bench automation tool based on the abstraction of the interface protocols. This tool will allow designers to describe their test benches in a high level language such as C rather than VHDL or Verilog. It helps designers to save their verification time and effort.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.990-994
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• 2003

This paper describes the VoIP(Voice over Internet Protocol) SoC(System on Chip) Design and the test board development for the function verification to support voice communication services using Internet. To implement the simple system of configuration, we designed the VoIP SoC which have ARM922T of 32bit microprocessor, IP network interface, voice signal interface, various user interface function. Also we developed test program and communication protocol to verify the function of this chip. We used several tools of design and simulation, developed and tested a test board with Excalibur which includes ARM922T microprocessor and FPGA.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1465-1469
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• 2003

In general satellite verification process, the AOCS (Attitude & Orbit Control Subsystem) should be verified through several kinds of verification test which can be divided into two major category like FBT (Fixed Bed Test) and polarity test. And each test performed in different levels such as ETB (Electrical Test Bed) and satellite level. The test method of FBT is to simulate satellite dynamics with sensors and actuators supported by necessary environmental models in ETB level. The VDS (Vehicle Dynamic Simulator) try to make the real situation as possible as the on-board processor will undergo after launch. The purpose of FBT test is to verify that attitude control logic function and hardware interface is designed as expected with closed loop simulation. The VDS is one of major equipments for performing FBT and consists of software and hardware parts. The VDS operates in VME environments with target board, several commercial boards and custom boards based on the VxWorks real time operating system. In order to make time synchronization between VDS and satellite on-board processor, high reliable semaphore was implemented to make synchronization with the interrupt signal from on-board processor. In this paper, the real-time operating environment used on VDS equipment is introduced, and the hardware and software configurations of VDS summarized in the systematic point of view. Also, we try to figure out the operational concept of VDS and AOCS verification test method with close-loop simulation.

• International Journal of Internet, Broadcasting and Communication
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• v.14 no.1
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• pp.1-9
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• 2022

Recently, a large number of cryptocurrencies and block chains have been continuously released. However, these cryptocurrencies and block chains are open to users without authorized verification and testing procedures, causing various reliability problems. Existing cryptocurrencies and blockchain test methods build a blockchain Testnet for a certain period of time by the developer without external verification by a third party, and after repeatedly self-testing and self-operating processes, commercialization is in progress by switching to the Mainnet. This self-verification method does not guarantee objectivity and publicness, and high reliability of customers cannot be realized. This study proposes a cryptocurrency and blockchain test interface and test control system as a third-party open test method.

• Advances in aircraft and spacecraft science
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• v.7 no.3
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• pp.251-269
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• 2020

Euclid is an optical/near-infrared survey mission of the European Space Agency (ESA) to investigate the nature of dark energy, dark matter and gravity by observing the geometry of the Universe and the formation of structures over cosmological timescales. The Euclid spacecraft mechanical architecture comprises the Payload Module (PLM) and the Service Module (SVM) connected by an interface structure designed to maximize thermal and mechanical decoupling. This paper shortly illustrates the mechanical system of the spacecraft and the mechanical verification philosophy which is based on the Structural and Thermal Model (STM), built at flight standard for structure and thermal qualification and the Proto Flight Model (PFM), used to complete the qualification programme. It will be submitted to a proto-flight test approach and it will be suitable for launch and flight operations. Within the overall verification approach crucial mechanical tests have been successfully performed (2018) on the SVM platform and on the sunshield (SSH) subsystem: the SVM platform static test, the SSH structure modal survey test and the SSH sine vibration qualification test. The paper reports the objectives and the main results of these tests.