A study on the generation of test benches from a C-like test scenario description

C 언어 중심의 테스트 시나리오 기술을 허용하는 테스트벤치 자동화 도구의 개발에 관한 연구

It is said that the verification effort occupies about 50-70 percent of the total effort of a System-On-A-Chip. This paper aims to develop a test bench automation tool based on the abstraction of the interface protocols. This tool will allow designers to describe their test benches in a high level language such as C rather than VHDL or Verilog. It helps designers to save their verification time and effort.