• 항공우주시스템공학회지
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• 제13권3호
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• pp.40-47
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• 2019

본 논문은 무인항공기 체계(UAS; unmanned aerial system)의 비행체 탑재장비 및 지상에서 운용하는 장비의 연동 검증을 위한 체계통합실험실(SIL; system integration laboratory) 및 체계통합시험(SIT; system integration test)의 환경 구축 및 이를 통한 검증방법에 대하여 다룬다. SIL 내 구축된 지상통제체계, 데이터링크체계, 비행체 탑재장비, 임무장비(EO/IR, SAR) 등과 같은 부체계간의 인터페이스 환경 및 모의 비행을 통한 체계 운용로직의 검증방법과 실험실 레벨에서의 검증이 완료된 각 부체계를 실제 시험 환경에서 검증하는 방법에 대해 기술한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.291-294
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• 2002

This paper proposed interface test method for performance verification of communication and broadcasting satellite between communication and broadcasting satellite payload and EGSE(Electrical Ground Support Equipment). We need ground support equipment for test them to performance verification and conform interface function of payload. This paper define tile telemetry transfer method for control payload using GSE(Ground Support Equipment) and receive telemetry data collected from GSE through bus simulator

• 한국철도학회논문집
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• 제7권2호
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• pp.114-119
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• 2004

According to the computerization of railway signalling systems. the communication protocol for interface between these systems are required. Therefore the new communication protocol for railway signaling system is required. Generally, there are two verification method for new designed protocol in the industrial and academic fields. One is the laboratory testing method which is very popular and general technique. In our research the comparison between existing and new designed protocol for signaling is described and the verification test results are also represented. From these laboratory test, we are verified the conformance of new designed protocol. Another method is verified by formal method. The format verification method is widely used at safety-critical system design but this approach is nor popular at verification communication protocol. However it is very important to verify the safety of new designed protocol for railway signaling system because signaling systems are very safety-critical systems. So, the methodology for formal verification of designed protocol is also reviews in this paper.

• 전자공학회논문지CI
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• 제43권4호
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• pp.39-49
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• 2006

본 논문에서는 차세대 입출력 인터페이스인, PCI 익스프레스 컨트롤러의 기능 검증을 위해 효율적인 검증 환경을 제안하였다. 검증 환경은 벡터 생성 부분, 테스트 벤치, 그리고 두개의 메모리로 구성된다. 이러한 효율적인 검증 환경을 제대로 동작시키기 위한 명령어 세트를 정의하였다. 이 명령어는 어셈블리 구조를 가지며, PCI 익스프레스의 모든 프로토콜을 지원하며, 설계된 PCI 익스프레스 컨트롤러를 검증하기 위한 모든 시나리오를 제공하도록 정의되었다. 또한 본 논문에서는 랜덤 벡터 생성 부분, 시뮬레이션 부분, 그리고 비교 엔진으로 구성된 랜덤 검증 환경을 제안하였다. 본 랜덤 테스트 검증 환경에서 수행된 결과는 일반적인 기본 동작 검증과 설계 기반 검증에서 찾지 못한 특수 경우의 에러도 발견 할 수 있다.

• 대한원격탐사학회:학술대회논문집
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• 대한원격탐사학회 2007년도 Proceedings of ISRS 2007
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• pp.544-547
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• 2007

Because data processing systems in recent years are more complicated, main function of the data processing is divided as several sub-functions which are implemented and verified in each subsystem of the data processing system. For the verification of data processing system, many interface tests among subsystems are required and also a lot of simulation systems are demanded. This paper proposes CTHS (Common Test Harness System) for satellite ground segment development which has all of functions for interface test of the data processing system in one PC. Main functions of the CTHS software are data interface, system log generation, and system information display. For the interface test of the data processing system, all of actions of the CTHS are executed by a pre-defined operation scenario which is written by purpose of the data processing system test.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.93-96
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• 2002

It is said that the verification effort occupies about 50-70 percent of the total effort of a System-On-A-Chip. This paper aims to develop a test bench automation tool based on the abstraction of the interface protocols. This tool will allow designers to describe their test benches in a high level language such as C rather than VHDL or Verilog. It helps designers to save their verification time and effort.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 추계종합학술대회
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• pp.990-994
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• 2003

본 논문은 인터넷을 이용한 음성통신 서비스를 제공하기 위해 사용되는 VoIP 시스템 칩 설계 및 기능 검증을 위한 보드 개발에 관한 것이다. 구성이 간단한 시스템을 구현하기 위하여 32비트 RISC 프로세서인 ARM922T 프로세서 코어를 중심으로 IP 망 접속 기능, 음성신호 접속 기능 및 다양한 사용자 정합 기능을 가지는 VoIP 시스템 칩을 설계하고, 이 칩의 기능을 검증하기 위하여 시험 프로그램 및 통신 프로토콜을 개발하였으며, 각종 설계 및 시뮬레이션 툴을 사용하고 ARM922T와 FPGA가 결합된 Excalibur를 사용한 시험용 보드를 개발하여 시험하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1465-1469
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• 2003

In general satellite verification process, the AOCS (Attitude & Orbit Control Subsystem) should be verified through several kinds of verification test which can be divided into two major category like FBT (Fixed Bed Test) and polarity test. And each test performed in different levels such as ETB (Electrical Test Bed) and satellite level. The test method of FBT is to simulate satellite dynamics with sensors and actuators supported by necessary environmental models in ETB level. The VDS (Vehicle Dynamic Simulator) try to make the real situation as possible as the on-board processor will undergo after launch. The purpose of FBT test is to verify that attitude control logic function and hardware interface is designed as expected with closed loop simulation. The VDS is one of major equipments for performing FBT and consists of software and hardware parts. The VDS operates in VME environments with target board, several commercial boards and custom boards based on the VxWorks real time operating system. In order to make time synchronization between VDS and satellite on-board processor, high reliable semaphore was implemented to make synchronization with the interrupt signal from on-board processor. In this paper, the real-time operating environment used on VDS equipment is introduced, and the hardware and software configurations of VDS summarized in the systematic point of view. Also, we try to figure out the operational concept of VDS and AOCS verification test method with close-loop simulation.

• International Journal of Internet, Broadcasting and Communication
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• 제14권1호
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• pp.1-9
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• 2022

Recently, a large number of cryptocurrencies and block chains have been continuously released. However, these cryptocurrencies and block chains are open to users without authorized verification and testing procedures, causing various reliability problems. Existing cryptocurrencies and blockchain test methods build a blockchain Testnet for a certain period of time by the developer without external verification by a third party, and after repeatedly self-testing and self-operating processes, commercialization is in progress by switching to the Mainnet. This self-verification method does not guarantee objectivity and publicness, and high reliability of customers cannot be realized. This study proposes a cryptocurrency and blockchain test interface and test control system as a third-party open test method.

• Advances in aircraft and spacecraft science
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• 제7권3호
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• pp.251-269
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• 2020

Euclid is an optical/near-infrared survey mission of the European Space Agency (ESA) to investigate the nature of dark energy, dark matter and gravity by observing the geometry of the Universe and the formation of structures over cosmological timescales. The Euclid spacecraft mechanical architecture comprises the Payload Module (PLM) and the Service Module (SVM) connected by an interface structure designed to maximize thermal and mechanical decoupling. This paper shortly illustrates the mechanical system of the spacecraft and the mechanical verification philosophy which is based on the Structural and Thermal Model (STM), built at flight standard for structure and thermal qualification and the Proto Flight Model (PFM), used to complete the qualification programme. It will be submitted to a proto-flight test approach and it will be suitable for launch and flight operations. Within the overall verification approach crucial mechanical tests have been successfully performed (2018) on the SVM platform and on the sunshield (SSH) subsystem: the SVM platform static test, the SSH structure modal survey test and the SSH sine vibration qualification test. The paper reports the objectives and the main results of these tests.