• Transactions on Electrical and Electronic Materials
• /
• v.18 no.6
• /
• pp.316-319
• /
• 2017

A new approach to improving the electrical characteristics and optical response of a polysilicon-based metal-semiconductor-metal (MSM) photodetector is proposed. To understand the cause of current restriction in the MSM photodetector, modified trap mechanisms are suggested, which include interfacial electron traps at the metal/polysilicon interface and silicon dangling bonds between silicon crystallite grains. Those traps were passivated using hydrogen ion implantation with subsequent post-annealing. Photodetectors that were ion-implanted under optima conditions exhibited improved photoconductivity and reduced dark current instability, implying that the hydrogen bonds in the polysilicon influence the simultaneous decreases in the density of dangling bonds at grain boundaries and the trapped positive charges at the contact interface.

• Proceedings of the Materials Research Society of Korea Conference
• /
• 2012.05a
• /
• pp.77.1-77.1
• /
• 2012

Zn 기반 산화물 반도체는 기존의 비정질 Si에 비해 저온공정에도 불구하고 높은 이동도, 투명하다는 장점으로 인해 차세대 디스플레이용 백플레인 소자로 주목받고 있다. 산화물 트랜지스터는 우수한 소자특성을 보여주고 있지만, 온도, 빛, 그리고 게이트 바이어스 스트레스에 의한 문턱전압의 불안정성이 문제의 문제를 해결해야한다. 산화물 반도체의 문턱전압의 불안정성은 유전체와 채널층의 계면 혹은 채널에서의 charge trap, photo-generated carrier, ads-/desorption of molecular 등의 원인으로 보고되고 있어, 고신뢰성의 산화물 채널층을 성장하기 위한 노력이 이루어지고 있다. 최근, 산화물 트랜지스터의 다양한 조건에서의 문턱전압의 불안정성을 해결하기 위해 산화물의 주된 결함으로 일컬어지고 있는 산소결핍을 억제하기 위해 성장공정의 제어 그리고, 산소와의 높은 binding energy를 같은 Al, Hf, Si 등과 같은 원소를 첨가하여 향상된 소자의 특성이 보고되고 있지만, 줄어든 산소공공으로 인해 이동도가 저하되는 문제점이 야기되고 있다. 이러한 문제점을 해결하기 위해, 최근에는 Buried layer의 삽입 혹은 bi-channel 등과 같은 방안들이 제안되고 있다. 본 연구는 atomic layer deposition을 이용하여 AZO bureid layer가 적용된 ZnO 트랜지스터의 특성과 안정성에 대한 연구를 하였다. 다결정 ZnO 채널은 유전체와의 계면에 많은 interface trap density로 인해 positive gate bias stress에 의한 문턱전압의 불안정성을 보였지만, AZO층이 적용된 ZnO 트랜지스터는 줄어든 interface trap density로 인해 향산된 stability를 보였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.06a
• /
• pp.239-242
• /
• 1998

Ca $F_2$ films have superior gate insulator properties than conventional gate insulator such as $SiO_2$, Si $N_{x}$, $SiO_{x}$, and T $a_2$ $O_{5}$ to the side of lattice mismatch between Si substrate and interface trap charge density( $D_{it}$). Therefore, this material is enable to apply Thin Film Transistor(TFT) gate insulator. Most of gate oxide film have exhibited problems on high trap charge density, interface state in corporation with O-H bond created by mobile hydrogen and oxygen atom. This paper performed Ca $F_2$ property evaluation as MIM, MIS device fabrication. Ca $F_2$ films were deposited at the various substrate temperature using a thermal evaporation. Ca $F_2$ films was grown as polycrystalline film and showed grain size variation as a function of substrate temperature and RTA post-annealing treatment. C-V, I-V results exhibit almost low $D_{it}$(1.8$\times$10$^{11}$ $cm^{-1}$ /le $V^{-1}$ ) and higher $E_{br}$ (>0.87MV/cm) than reported that formerly. Structural analysis indicate that low $D_{it}$ and high $E_{br}$ were caused by low lattice mismatch(6%) and crystal growth direction. Ca $F_2$ as a gate insulator of TFT are presented in this paper paperaper

• Proceedings of the Korean Vacuum Society Conference
• /
• 2012.02a
• /
• pp.340-340
• /
• 2012

최근 MOS 소자들이 게이트 산화막을 Mono-layer가 아닌 Multi-Layer을 사용하는 추세이다. Bulk와 High-k물질간의 Dangling Bond를 줄이기 위해 Passivation 층을 만드는 것을 예로 들 수 있다. 이러한 Double Layer의 쓰임이 많아지면서 계면에서의 Interface State Density의 영향도 커지게 되면서 이를 측정하는 방법에 대한 연구가 활발히 진행되고 있다. 본 연구에서는 $SiO_2$ Double Layer의 Interface State Density를 Conductance Method를 사용하여 구하는 연구를 진행하였다. Wet Oxidation과 Chemical Vapor Deposition (CVD) 공정을 이용하여 $SiO_2$ Double-layer로 증착한 후 Aluminium을 전극으로 하는 MOS-Cap 구조를 만들었다. 마지막 공정은 $450^{\circ}C$에서 30분 동안 Forming-Gas Annealing (FGA) 공정을 진행하였다. LCR meter를 이용하여 high frequency C-V를 측정한 후 North Carolina State University California Virtual Campus (NCSU CVC) 프로그램을 이용하여 Flatband Voltage를 구한 후에 Conductance Method를 측정하여 Dit를 측정하였다. 본 연구 결과 Double layer (Wet/CVD $SiO_2$)에 대해서 Conductance Method를 방법을 이용하여 Dit를 측정하는 것이 유효하다는 것을 확인 할 수 있었다. 본 실험은 앞으로 많이 쓰이고 측정될 Double layer (Wet/CVD $SiO_2$)에 대한 Interface State Density의 측정과 분석에 대한 방향을 제시하는데 도움이 될 것이라 판단된다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.20 no.10
• /
• pp.859-863
• /
• 2007

Aluminum oxide films were deposited on n-type 6H-SiC(0001) substrates by RF magnetron sputtering technique for MIS devices applications. Well-behaved C-V characteristics were obtained measured in MIS capacitors structures. The calculated interface trap density measured at $300^{\circ}C$ was about $4.6{\times}10^{10}/cm^2\;eV$ in the upper half of the bandgap. The gate leakage current densities of the MIS structures were about $10^{-8}A/cm^2$ and about $10^{-6}A/cm^2$ measured at room temperature and at $300^{\circ}C$ for a ${\pm}1\;MV/cm$, respectively These results indicate that the interface property of this structure is enough quality to MIS devices applications.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.21 no.4
• /
• pp.329-334
• /
• 2008

Aluminum oxide films were deposited on n-type GaN substrates by RF magnetron sputtering technique for MIS devices applications using optimized conditions, Well-behaved C - V characteristics were obtained measured in MIS capacitors structures. The calculated interface trap density measured at $300^{\circ}C$ was about $9\times10^{10}/cm^2$ eV in the upper bandgap. The gate leakage current densities of the MIS structures were about $10^{-9}A/cm^2$ and about $10^{-4}A/cm^2$ measured at room temperature and at $300^{\circ}C$ for $a{\pm}1MV/cm$, respectively. These results indicate that the interface property of this structure is enough quality to MIS devices applications.

• Transactions on Electrical and Electronic Materials
• /
• v.17 no.1
• /
• pp.25-28
• /
• 2016

We investigate the effect of interface states on the endurance of a charge trap flash (CTF) NOR array using charge pumping methods. The endurance test was completed from one cell selected randomly from 128 bit cells, where the memory window value after 10² program/erase (P/E) cycles decreased slightly from 2.2 V to 1.7 V. However, the memory window closure abruptly accelerated after 10³ P/E cycles or more (i.e. 0.97 V or 0.7 V) due to a degraded programming speed. On the other hand, the interface trap density (Nit) gradually increased from 3.13×10¹¹ cm⁻² for the initial state to 4×10¹² cm⁻² for 10² P/E cycles. Over 10³ P/E cycles, the Nit increased dramatically from 5.51×10¹² cm⁻² for 10³ P/E cycles to 5.79×10¹² cm⁻² for 10⁴ P/E cycles due to tunnel oxide damages. These results show good correlation between the interface traps and endurance degradation of CTF devices in actual flash cell arrays.

• Proceedings of the KIEE Conference
• /
• 1993.07b
• /
• pp.1268-1270
• /
• 1993

In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.37 no.1
• /
• pp.101-105
• /
• 2024

4H-SiC power metal-oxide-semiconductor field effect transistors (MOSFETs) have been developed to achieve lower specific-on-resistance (R_on,sp), and the gate oxides have been thermally grown. The poor channel mobility resulting from the high interface trap density (D_it) at the SiO₂/4H-SiC interface significantly affects the higher switching loss of the power device. Therefore, the development of novel fabrication processes to enhance the quality of the SiO₂/4H-SiC interface is required. In this paper, NO post-oxidation annealing (POA) by using the conditions of N₂ diluted NO at a high temperature (1,300℃) is proposed to reduce the high interface trap density resulting from thermal oxidation. The NO POA is carried out in various NO ambient (0, 10, 50, and 100% NO mixed with 100, 90, 50, and 0% of high purity N₂ gas to achieve the optimized condition while maintaining a high temperature (1,300℃). To confirm the optimized condition of the NO POA, measuring capacitance-voltage (C-V) and current-voltage (I-V), and time-of-flight secondary-ion mass spectrometry (ToF-SIMS) are employed. It is confirmed that the POA condition of 50% NO at 1,300℃ facilitates the equilibrium state of both the oxidation and nitridation at the SiO₂/4H-SiC interface, thereby reducing the D_it.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2015.08a
• /
• pp.212.1-212.1
• /
• 2015

본 연구에서는 용액 공정을 통해 제작한 IGZO 박막 트랜지스터의 Active layer를 적층 구조로 쌓아올리고, 신뢰성 평가를 위해 Gate에 지속적인 바이어스를 인가함으로써 소자의 문턱 전압 변화를 측정 실험을 진행하였다. Active layer 제작에 사용된 용액의 비율은 In:Zn:Ga = 1:1:30%로 제작되었고, 단일층부터 이중, 삼중층까지 적층을 하였다. 각 소자의 Active layer 층이 많아질수록 이동도가 1.21, 0.87, 0.69 ($cm^2/Vs$)으로 감소하는 등의 전기적 특성이 감소하는 경향을 보였다. 하지만 Gate에 10 V를 3000초간 지속적으로 인가해주었을 때 문턱 전압의 변화가 단일층일 때 10.4 V에서 삼중층일 때 1.3 V로 감소하였다. 이것은 Active layer의 층 사이의 계면이 형성되면서 current path에 영향을 주어 전기적 특성이 감소하였지만, 적층으로 인한 surface의 uniformity가 향상되는 것으로 확인하였다. 또한 1500초에서 Dit (Interface Trap Density)를 추출한 결과, 단일층에서는 $7.53{\times}10^{12}$($cm^{-2}-1$<)로 삼중층에서 $4.52{\times}10^{12}$($cm^{-2}-1$<)의 약 두 배 정도 높게 추출되었다.