• 전자공학회논문지A
• /
• 제33A권10호
• /
• pp.186-194
• /
• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• 한국통신학회논문지
• /
• 제21권11호
• /
• pp.2739-2749
• /
• 1996

This aper introduces the multiple Neocognitron module approach for the effective target reognition. The Neocognitron which is designed to classify a pattern by extracting the local features from it, seems to be an unique method that can perform a pattern recognition using the neural networks. But due to its rigid structure, the Neocognitron must be reconstructed whenever there exists a variation on the number of classes. This is a quite difficult problem for the target recognition application that needs huge amount of computation and numerous classes to be classified. In this paper, we construct several smaller Necognitrom modules and train each module to adapt each class. After construction of the mulules, we integrate them in parallel so as to adaopt input at the same time and to produce each score that shold be matched to be learned class. This approach can reduce the sizes of the networks and is adaptive to the increase of classes as well as the authentic distortion, shift, scale variation and slight rotation invariant properties of general Neocognitron. This paper show the effectiveness of the proposed approach through some experience and performs analysis of the inhibitory interconnections in the architecture of the multiple module structure.

• 한국통신학회논문지
• /
• 제18권3호
• /
• pp.410-424
• /
• 1993

본 논문에서 디지털 신호처리를 위한 시스톨릭 배열과 비동기 제어 설계를 새로운 기법에 대하여 작성하였다. 특히, 배열안에 사전에 데이터를 입력하는 방법이나, 전체적인 제어와 같은 예전 방법과 다르게 최적의 성능을 성취할 수 있는 간단하고 내부적인 상호 연결을 갖는 시스톨릭 배열을 제안하고 있다. 이와 같은 디지털 신호처리에 대한 비동기 시스톨릭 배열은 일정하게 설계된 배열에서 비교한 경우 전체 계산 시간을 상당히 줄일 수 있음을 비교를 통해서 다루었다. 비동기 시스톨릭 배열의 중요한 요소는 입력 데이터를 적절하고 효율적으로 제어할 수 있는 통신 프로토콜 설계이다. 마지막으로, Transputer의 병렬 컴퓨터 언어인 OCCAM를 이용하여 배열의 효율성을 비교 분석하고 시뮬레이션의 결과를 보였다.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.149-149
• /
• 2008

Metal-Insulator-Metal(MIM) capacitors have been studied extensively for next generation of high-density dynamic random access memory (DRAM) devices. Of several candidates for metal electrodes, Ru or its conducting oxide $RuO_2$ is the most promising material due to process maturity, feasibility, and reliability. ALD can be used to form the Ru and RuO2 electrode because of its inherent ability to achieve high level of conformality and step coverage. Moreover, it enables precise control of film thickness at atomic dimensions as a result of self-limited surface reactions. Recently, ALD processes for Ru and $RuO_2$, including plasma-enhanced ALD, have been studied for various semiconductor applications, such as gate metal electrodes, Cu interconnections, and capacitor electrodes. We investigated Ru/$RuO_2$ thin films by thermal ALD with various deposition parameters such as deposition temperature, oxygen flow rate, and source pulse time. Ru and $RuO_2$ thin films were grown by ALD(Lucida D150, NCD Co.) using RuDi as precursor and O2 gas as a reactant at $200\sim350^{\circ}C$.

• 대한전자공학회논문지SD
• /
• 제47권5호
• /
• pp.48-55
• /
• 2010

반도체 설계기술의 발달로 구현 회로가 복잡해지고, 동작속도가 크게 증가함에 따라, 반도체 이후 (post-silicon) 설계 단계에서 repair를 위한 기간 및 비용이 크게 증가하고 있다. 본 논문에서는 예비 셀을 이용한 repair 방법을 통해 설계 오류로 인한 repair시 혹은 설계 변경 시에 전체 재설계를 최소화하는 방법을 제안하였다. 또한 예비 셀을 이용한 설계 변경 과정에서 repair layer에 설계 변경을 국한하여 mask 비용과 time-to-market을 줄이는 방법을 개발하였다. 또한 회로 분할을 통해 repair 과정에서 사용하는 예비회로의 비용을 줄일 수 있도록 한다.

• 한국원자력학회:학술대회논문집
• /
• 한국원자력학회 1996년도 추계학술발표회논문집(1)
• /
• pp.191-196
• /
• 1996

The potential value of the Application Specific Integrated Circuits(ASIC's) in safety systems of Nuclear Power Plants(NPP's) is being increasingly recognized because they are essentially hardwired circuitry on a chip, the reliability of the system can be proved more easily than that of software based systems which is difficult in point of software V&V(Verification and Validation). There are two types of ASIC, one is a full customized type, the other is a half customized type. PLD(Programmable Logic Device) used in this paper is a half customized ASIC which is a device consisting of blocks of logic connected with programmable interconnections that are customized in the package by end users. This paper describes the RPS(Reactor Protection System) composed of ASICs which provides emergency shutdown of the reactor to protect the core and the pressure boundary of RCS(Reactor Coolant System) in NPP's. The RPS is largely composed of five logic blocks, each of them was implemented in one PLD, as the followings. A). Bistable Logic B). Matrix Logic C).Initiation Logic D). MMI(Man Machine Interface) Logic E). Test Logic.

• 동의생리병리학회지
• /
• 제30권6호
• /
• pp.402-411
• /
• 2016

The concept of the meridian system is originated from an empirical, systematic references in the clinical setting, which does not always require anatomical features. As the principles of systems biology are mainly associated with regulating the body's internal environment to maintain a stable condition, they are closely similar to the theory of the meridian system. In this review, I describe the origin of the concept of the meridian system, current status of research on the meridian system and acupuncture points, and the future directions of the research. To unravel the entity of the meridian system, we have to start from understanding its origin and clinical significance. The meridian system, as a theoretical model of the indications of acupuncture points, can help to understand the interconnections that underlie the pathologies of particular diseases or symptoms. Based on the establishment of clinical data platform for acupuncture research, we can extract novel medical information from the clinical data and generate analytical models that are useful for medical knowledge discovery on acupuncture points in the future.

• 한국정밀공학회지
• /
• 제20권10호
• /
• pp.183-190
• /
• 2003

Major device failures such as die cracking, interfacial delamination and warpage in flip chip packages are due to excessive heat and thermal gradients- There have been significant researches toward understanding the thermal performance of electronic packages, but the majority of these studies do not take into account the combined effects of thermo-mechanical interactions of the different package constituents. This paper investigates the thermo-mechanical performance of flip chip package constituents based on the finite element method with thermo-mechanically coupled elements. Delaminations with different lengths between the silicon die and underfill resin interfaces were introduced to simulate the defects induced during the assembly processes. The temperature gradient fields and the corresponding stress distributions were analyzed and the results were compared with isothermal case. Parametric studies have been conducted with varying thermal conductivities of the package components, substrate board configurations. Compared with the uniform temperature distribution model, the model considering the temperature gradients provided more accurate stress profiles in the solder interconnections and underfill fillet. The packages with prescribed delaminations resulted in significant changes in stress in the solder. From the parametric study, the coefficients of thermal expansion and the package configurations played significant roles in determining the stress level over the entire package, although they showed little influence on stresses profile within the individual components. These observations have been implemented to the multi-board layer chip scale packages (CSP), and its results are discussed.

• 한국진공학회:학술대회논문집
• /
• 한국진공학회 1995년도 제9회 학술발표회 논문개요집
• /
• pp.48-49
• /
• 1995

전자소자의 축소화에 따라 electromigration은 점차 반도체 디바이스의 주요 결함 원 인으로 부각되고 있다. 본 실험은 현재 배선 재료로 널리 사용되고 있는 Al-1%Si 금속박막 배선의 electromigration에 대한 온도 및 배선길이 의존성에 관하여 연구하였다. ppLCC(pplastic Leaded Chipp Carrier) ppackage된 ppSG(8000$\AA$)/SiO2(1000$\AA$)/Al-1%Si(7000 $\AA$)/SiO2(5000$\AA$)/pp-typpe Si(100)의 보호막처리된 시편과 Al-1%Si/SiO2(5000$\AA$)/pp-typpe Si(100)의 보호막처리되지 않은 시편등을 standard pphotolithograpphy 공정을 이용하여 각각 제작하였다. 선폭 3$mu extrm{m}$, 길이 100, 400, 800, 1600$\mu\textrm{m}$의 등의 Al-1%Si 박막배선구조를 사용하 였다. 가속화실험을 위해 인가된 D.C 전류밀도는 4.5$\times$106A/cm2이었고 실온에서 10$0^{\circ}C$까지 의 분위기 온도에서 electromigration를 실행하였다. 박막배선길이에 따른 MTF(Mean Time-to-Failure)는 임계길이 이상에서 포화되는 경향을 보이며 임계길이는 Al-1%Si 박막 배선에서 분위기온도에 따라 길이 400$\mu\textrm{m}$과 800$\mu\textrm{m}$범위에서 나타났다. 각 시편에서 electromigration에 대한 활성화에너지도 MTF의 특성과 유사하게 임계길이 이상에서 포화 되는 특성을 타나내었다.

• 전자공학회논문지A
• /
• 제32A권12호
• /
• pp.184-197
• /
• 1995

In this paper, high speed IC package-to-package interconnections are modeled as lossless multiconductor transmission lines operating in the TEM mode. And, three mathematical algorithms for computing electrical parameters of the lossless multiconductor transmission lines are described. A semi-analytic Green's function method is used in computing per unit length capacitance and inductance matrices, a matrix square root algorithm based on the QR algorithm is used in computing a characteristic impedance matrix, and a matrix algorithm based on the theory of M-matrix is used in computing a diagonally matched load impedance matrix. These algorithms are implemented in a computer program DIME (DIagonally Matched Load Impedance Extractor) which computes electrical parameters of the lossless multiconductor transmission lines. Also, to illustrate the concept of design database for high speed IC package-to-package interconnection, a database for the multi conductor strip transmission lines system is constructed. This database is constructed with a sufficiently small number of nodes using the multi-dimensional cubic spline interpolation algorithm. The maximum interpolation error for diagonally matched load impedance matrix extraction from the database is 1.3 %.