• Journal of Power Electronics
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• v.12 no.5
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• pp.708-714
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• 2012

This paper presents a new interleaved pulse-width modulation (PWM) boost-flyback converter to achieve power factor correction (PFC) and regulate DC bus voltage. The adopted boost-flyback converter has a high voltage conversion ratio to overcome the limit of conventional boost or buck-boost converter with narrow turn-off period. The proposed converter has wide turn-off period compared with a conventional boost converter. Thus, the higher output voltage can be achieved in the proposed converter. The interleaved PWM can further reduce the input and output ripple currents such that the sizes of inductor and capacitor are reduced. Since boundary conduction mode (BCM) is adopted to achieve power factor correction, power switches are turned on at zero current switching (ZCS) and switching losses are reduced. The circuit configuration, principle operation, system analysis, and design consideration of the proposed converter are presented in detail. Finally, experiments conducted on a laboratory prototype rated at 500W were presented to verify the effectiveness of the converter.

• Proceedings of the KIEE Conference
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• 2003.07b
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• pp.979-981
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• 2003

A novel single-stage power factor corrected (PFC) drive for switched reluctance motor (SRM) is presented to achieve sinusoidal, near unity power factor input current. The proposed PFC SRM drive has no additional active switch. And a single-stage approach, which combines a DC link capacitor used as do source and a drive used for driving the motor into one power stage, has a simple structure and low cost. The characteristics and validity of the proposed circuit will be discussed in depth through the experimental results.

• Proceedings of the KIPE Conference
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• 2001.07a
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• pp.594-599
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• 2001

A study of single-stage PFC electronic ballast with constant do-link voltage is presented in this paper. The proposed ballast is combined by two interleaved boost cells and a conventional half bridge dc/ac inverter, By exploiting the interleaving technique, the Input ripple current of the electronic ballast is reduced. Theoretical analysis and experimental results for two 45(W) fluorescent lamps are presented.

• Proceedings of the KIPE Conference
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• 2016.11a
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• pp.117-118
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• 2016

본 논문은 입력 전류 리플이 없고 낮은 스위치 전압 스트레스를 갖는 고승압 부스트-세픽 DC-DC 컨버터를 제안한다. 제안된 컨버터는 부스트 단의 보조회로에 의해 입력 전류 리플이 상당히 제거되었으며 세픽 단에 결합 인덕터를 적용하여 높은 전압 이득을 달성하였다. 또한 스위치 전압 스트레스는 클램핑 회로에 의해 감소되었으며 따라서 상대적으로 낮은 $R_{ds(on)}$ 갖는 MOSFET을 사용하여 컨버터의 효율이 개선되었다. 추가적으로 결합 인덕터의 누설 인덕터로 인하여 출력 다이오드의 역회복 손실이 완화되었다. 제안된 컨버터는 이론적 해석과 200[V]-200[W]하드웨어 시작품을 제작하여 검증하였다.

• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.74-75
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• 2010

As global warming due to burning fossil fuels and natural resource depletion issues have emerged, the development of renewable energy sources such as photovoltaics (PV) has been brought to recent interest. Amongst the vast efforts to harvest and convert solar energy into electricity, the module integrated converters (MIC) has become a worthy topic of research for grid-connected photovoltaic systems. Due to the required high-boosting qualities, only a restricted amount of DC/DC converter topologies can be applied to MICs. This paper investigates the possibility of a tapped-inductor boost converter as a candidate for PV MICs. A dual-inductor interleaving scheme operating slightly above the boundary of the two conduction modes (BCM) is suggested for reduction of input current ripple and minimization of component stress. A digital controller is used for implementation, assuring maximum power tracking and transfer while providing sufficient computational space for other grid connectivity applications, etc. For verification, a 200W converter is designed and simulated via computer software including component losses. High efficiency over a wide power range proves the feasibility of the proposed PV MIC system.

• Journal of Power Electronics
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• v.17 no.4
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• pp.884-891
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• 2017

The improved transfer functions of the modified Sheppard-Taylor (MS-T) converter, which is capable of regulating output voltage under a wide range of input voltage and load variations, negligible current ripple, and fewer components in comparison to the Sheppard-Taylor (S-T) converter, operating in continuous conduction mode (CCM) are investigated in this study. Its DC equilibrium point, small signal model, and transfer functions are derived and analyzed. Then, the voltage controller is applied for this MS-T converter. The comparisons between the derived model and the existing model are presented. The hardware circuit is designed and the circuit experiments are provided for validation. The results show that the improved transfer functions of the MS-T converter are more effective and general than the previous ones for describing its real characteristics.

• The Transactions of the Korean Institute of Power Electronics
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• v.16 no.3
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• pp.209-218
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• 2011

In low voltage high current applications such as fuel cells the current-fed DC-DC converter which has small ripple current and turn ratio is more efficient. In the applications larger than 5kW the conventional single-phase current-fed converter based on full-bridge, half-bridge or push-pull topologies has high current burden of devices such as switches, and the selection and optimized design of the devices are not easy. In this paper a three-phase active-clamped current-fed push-pull DC-DC converter suitable for high power high step-up applications is proposed. The proposed converter has reduced current burden and is suitable for wide input voltage applications due to the use of whole duty cycle range. Design methods of main components including three-phase high frequency transformers are provided, and the validity and performance of the proposed converter are proved from a 5kW prototype.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.7A
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• pp.568-573
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• 2009

This paper presents a step-down DC-DC converter with On-chip Compensation for battery-operated portable electronic devices which are designed in O.13um CMOS standard process. In an effort to decrease system volume, this paper proposes the on chip compensation circuit using capacitor multiplier method. Capacitor multiplier method can minimize error amplifier's compensation capacitor size by 10%. It allows the compensation block of DC-DC converter be easily integrated on a chip and occupy less layout area. But capacitor multiplier operation reduces DC-DC converter efficiency. As a result, this converter shows maximum efficiency over 87.2% for the output voltage of 1.2V (input voltage : 3.3V), maximum load current 500mA, and 25mA output ripple current. This voltage mode controled buck converter has 1MHz switching frequency.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.5
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• pp.384-390
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• 2022

In this study, a single-stage, four-phase, interleaved, totem-pole AC-DC converter is proposed for a super-fast charger station that requires high power, a wide voltage range, and bidirectional operation capabilities and adopts various types of electric transport vehicles. The proposed topology is based on current-fed push-pull dual active bridge converter combined with the totem-pole operation. Owing to the four-phase interleaving effect, the bridge on the grid side can switch at 0.25, 0.5, and 0.75 to achieve a ripple-free grid current. The input filter can be removed theoretically. Switching methods for the duty of the secondary-side duty cycle are proposed, and they correspond to the primary duty cycle for reducing the circulating power and handling the total harmonic distortion. Therefore, the converter can operate under a wide voltage range. Experimental results from a 7.5 kW prototype are used to validate the proposed concept.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.6
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• pp.57-65
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• 2007

This paper presents the design of single phase PFC(Power Factor Correction) using a DSP(TMS320F2812). In order to realize the proposed boost PFC converter in average current mode control, the DSP requires the A/D sampling values for a line input voltage, a inductor current, and the output voltage of the converter. Because of a FET switching noise, these sampling values contain a high frequency noise and switching ripple. The solution of A/D sampling keeps away from the switching point. Because the PWM duty is changed from 5% to 95%, we can#t decide a fixed sampling time. In this paper, the three A/D converters of the DSP are started using the prediction algorithm for the FET ON/OFF time at every sampling cycle(40 KHz). Implemented A/D sampling algorithm with only one timer of the DSP is very simple and gives the autostart of these A/D converters. From the experimental result, it was shown that the power factor was about 0.99 at wide input voltage, and the output ripple voltage was smaller than 5 Vpp at 80 Vdc output. Finally the parameters and gains of PI controllers are controlled by serial communication with Windows Xp based PC. Also it was shown that the implemented PFC converter can achieve the feasibility and the usefulness.