• Title/Summary/Keyword: Input buffer

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A Study on the Linear Counting Ratemeter (선형 계수율계에 관한 연구)

  • 이병선
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.8 no.6
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    • pp.8-16
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    • 1971
  • This paper describes the transistorized linear counting ratemeter which can be uses to indicate on the meter or record the counting rates of the nuclear radiations produced from the atomic reactor or from the radio isotopes. Tte feature of this ratemeter is the use of the transistor chopper for good stabilization. At the input stage of the a. c. amplifier a composite emitter follower buffer stage has been used to give the high input impedance. A hybrid parameter equivalent circuit was modeled for the analysis of this buffer stage. The counting rates can be linearly measured from few CPS up to 100KCPS in 4 ranges. The resolution is less than 0.5$\mu$sec and the output drift at the room temperature with 7-hour continuous operation is in the order of $\pm$0.5$\mu$A.

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Quantitative Assessment of Input and Integrated Information in GIS-based Multi-source Spatial Data Integration: A Case Study for Mineral Potential Mapping

  • Kwon, Byung-Doo;Chi, Kwang-Hoon;Lee, Ki-Won;Park, No-Wook
    • Journal of the Korean earth science society
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    • v.25 no.1
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    • pp.10-21
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    • 2004
  • Recently, spatial data integration for geoscientific application has been regarded as an important task of various geoscientific applications of GIS. Although much research has been reported in the literature, quantitative assessment of the spatial interrelationship between input data layers and an integrated layer has not been considered fully and is in the development stage. Regarding this matter, we propose here, methodologies that account for the spatial interrelationship and spatial patterns in the spatial integration task, namely a multi-buffer zone analysis and a statistical analysis based on a contingency table. The main part of our work, the multi-buffer zone analysis, was addressed and applied to reveal the spatial pattern around geological source primitives and statistical analysis was performed to extract information for the assessment of an integrated layer. Mineral potential mapping using multi-source geoscience data sets from Ogdong in Korea was applied to illustrate application of this methodology.

A Wideband Inductorless LNA for Inter-band and Intra-band Carrier Aggregation in LTE-Advanced and 5G

  • Gyaang, Raymond;Lee, Dong-Ho;Kim, Jusung
    • Journal of IKEEE
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    • v.23 no.3
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    • pp.917-924
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    • 2019
  • This paper presents a wideband low noise amplifier (LNA) that is suitable for LTE-Advanced and 5G communication standards employing carrier aggregation (CA). The proposed LNA encompasses a common input stage and a dual output second stage with a buffer at each distinct output. This architecture is targeted to operate in both intra-band (contiguous and non-contiguous) and inter-band CA. In the proposed design, the input and second stages employ a gm enhancement with resistive feedback technique to achieve self-biasing, enhanced gain, wide bandwidth as well as reduced noise figure of the proposed LNA. An up/down power controller controls the single input single out (SISO) and single input multiple outputs (SIMO) modes of operation for inter-band and intra-band operations. The proposed LNA is designed with a 45nm CMOS technology. For SISO mode of operation, the LNA operates from 0.52GHz to 4.29GHz with a maximum power gain of 17.77dB, 2.88dB minimum noise figure and input (output) matching performance better than -10dB. For SIMO mode of operation, the proposed LNA operates from 0.52GHz to 4.44GHz with a maximum voltage gain of 18.30dB, a minimum noise figure of 2.82dB with equally good matching performance. An $IIP_3$ value of -6.7dBm is achieved in both SISO and SIMO operations. with a maximum current of 42mA consumed (LNA+buffer in SIMO operation) from a 1.2V supply.

Electrical Properties of Traveling-wave Coplanar Waveguide Transmission Line with a Abruptly broken Input-Output-taper for $LiNbO_3$Optical Modulator Electrode (급격히 꺾인 Taper를 갖는 Traveling-wave Coplanar Waveguide형 $LiNbO_34$전기광학변조기 전송선로의 전기적 특성)

  • 정운조;김성구
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.13 no.12
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    • pp.1051-1057
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    • 2000
  • A traveling-wave CPW(coplanar waveguide) electrode with abruptly broken input/output-taper for LiNbO$_3$optical modulator was designed and fabricated. The electrical characteristics of traveling-wave electrode on z-cut LiNbO$_3$crystal with SiO$_2$buffer layers were measured by network analyzer. To confirm the possibility of the electro-optic modulator electrode, detailed calculations of the impedance, microwave effective index and attenuation constants are presented as a function of the microwave electrode thickness, but the buffer layer thickness is fixed as 1${\mu}{\textrm}{m}$. These characteristics are discussed from the viewpoint of the device optimization and are expected to be design guides for the LiNbO$_3$modulator’s electrodes.

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A 4-Channel 6.25-Gb/s/ch VCSEL Driver for HDMI 2.0 Active Optical Cables

  • Hong, Chaerin;Park, Sung Min
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.4
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    • pp.561-567
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    • 2017
  • This paper presents a 4-channel common-cathode VCSEL driver array operating up to 6.25 Gb/s per channel for the applications of HDMI 2.0 active optical cables. The proposed VCSEL driver consists of an input buffer, a modified Cherry-Hooper amplifier as a pre-driver, and a main driver with pre-emphasis to drive a common-cathode VCSEL diode at high-speed full switching operations. Particularly, the input buffer merges a linear equalizer not only to broaden the bandwidth, but to reduce power consumption simultaneously. Measured results of the proposed 4-channel VCSEL driver array implemented in a $0.13-{\mu}m$ CMOS process demonstrate wide and clean eye-diagrams for up to 6.25-Gb/s operation speed with the bias current 2.0 mA and the modulation currents of $3.1mA_{PP}$. Chip core occupies the area of $0.15{\times}0.1{\mu}m^2$ and dissipate 22.8 mW per channel.

Performance Analysis of the Network Access Subsystem in AICPS Using Hybrid Simulation (Hybrid 시뮬레이션을 이용한 대용량 통신처리시스템의 정합장치에 대한 성능분석)

  • 김지수
    • Journal of the Korea Society for Simulation
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    • v.8 no.2
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    • pp.1-11
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    • 1999
  • Advanced information communication processing system mainly consists of network access subsystems and a switching system. This paper provides performance analysis of a typical network access subsystem. The network access subsystem is modeled as a queueing network including a server providing polling services. The arrival process of messages to an input buffer is regarded as a Poisson process. Performance measures such as mean input buffer length and mean waiting time of meassages are obtained through simulation, for it is impossible to calculate the performance measures using an analytical method. Hybrid simulation is used to reduce the variance of estimators. The variance reduction effect on the mean waiting time is reported.

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PERFORMANCE ANALYSIS OF A MULTIPLEXER WITH THE THRESHOLD BASED OVERLOAD CONTROL IN ATM NETWORKS

  • Park, Chul-Geun
    • Journal of applied mathematics & informatics
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    • v.5 no.3
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    • pp.643-658
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    • 1998
  • In this paper we analyze the performance of a statistical ATM multiplexer with bursty input traffic and two thresholds in the buffer by using queueing model. Two priority levels are considered for source traffic which is modeled by Markov Modulated Poisson Process to represent the bursty characteristics. Service time distributions of two priority sources are assumed to be same and deterministic for ATM environment. The partial buffer sharing scheme with one threshold may experience a sensitive state change around the threshold. But the proposed multiplexer with two thresholds avoids this hysterical phenominon to improve the system operation.

Cell Scheduling Scheme for Multimedia Service in ATM Network (ATM망에서 멀티미디어 서비스를 위한 셀 스케줄링 기법)

  • 김남희;전병실
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.11C
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    • pp.94-101
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    • 2001
  • In this paper, we propose WRR cell scheduling algorithm that improve current smoothing scheme. In proposed cell scheduling algorithm, using the number of practical input cell in each VC and variable thats indicate weight and state of queue, we could service VC of buffer efficiently that input cells over weight value and input cells smaller than weight value. And, we could service multimedia data by providing remained bandwidth after that allocate to real time traffic with non-real time traffic. In this result, the number of serviceable average cells were increased and length of buffer was decreased. Through the computer simulation, we evaluated the performance of proposed algorithm. According to the results, the proposed algorithm showed good performance.

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An input-buffer ATM switch based on the dynamic change of the threshold for the occupancy of the buffer (버퍼에 설정된 점유 임계치의 동적 변화에 기초한 입력버퍼형 ATM 스위치)

  • Paik, Jung-Hoon;Lim, Chae-Tak
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.36S no.2
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    • pp.19-27
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    • 1999
  • This paper propose a contention resolution policy featuring dynamic change of the threshold for the occupancy of the input buffer for an input buffering ATM switching architecture and its hardware implementation strategy. The strategy is provided with the aim of the simple structure that achieves the reduction of the signal path and the power consumption. The threshold is changed dynamically every time slot based both the arrived of cells and the cell service resulting from the contention resolution. The performance on the cell loss of the proposed policy is performed and compared with the conventional policy under the diverse traffic conditions through both the analysis based ont the Markov chain and the simulation.

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FPGA Design of Adaptive Digital Receiver for Wireless Identification (무선인식을 위한 적응적 디지털 수신기의 FPGA 설계)

  • Seo Young-Ho;Kim Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.9 no.4
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    • pp.745-752
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    • 2005
  • In this paper we propose and implement a digital part of a receiver system for identifying a moving object and its tracking position in wireless environment. We assumed UWB(Ultra Wide Band)-based communication system for target application and used serial communication method(RS-232). The proposed digital receiver consists of RS-232-type1/RS-232-type2 for input and output of serial communication, ID Detector for detecting IDs, and PISO&Buffer circuit to buffer input signals for appropriate operation of ID Detector. We implemented the digital receiver with minimal hardware(H/W) resource according to target application of UWB-based communication system. So it correlates input patterns with pre-stored patterns though repeated detecting method for multiple IDs. Since it has reference panerns in the Ve-stored form, it can detect various IDs instantly. Also we can program content and size of reference patterns considering compatibility with other systems .The implemented H/W was mapped into XC2S100PQ208-5 FPGA of Xilinx, occupied 727($30\%$) cells, and stably operated in the clock frequency of 75MHz(13.341ns).