• The KIPS Transactions:PartC
• /
• v.12C no.7 s.103
• /
• pp.1031-1038
• /
• 2005

As the research on home network technologies, sensor network technologies, and ubiquitous network technologies makes rapid progresses, wireless ad-hoc network have attracted a lot of attention. A wireless ad-hoc network is a temporary network formed by a collection of wireless mobile nodes without the aid of my existing network infrastructure or centralized administration, and it is suitable for ubiquitous computing environments. In this paper, we suggest an interconnection scheme between the wireless ad-hoc network environment based on multiple path source routing protocol and a Mobile-IP based network environment. This scheme reduces the overhead of route re-establishment and re-registration by maintaining multiple paths between the mobile host in wireless ad-hoc network and the base station in mobile-IP network. Also it puts the base station in charge of function that performs translation between wireless ad-hoc network packets and Mobile-IP packets, reducing the load of mobile hosts. In this paper, our simulations show that our scheme outperforms existing interconnecting schemes with regards to throughput and end-to-end delay Also we show that our scheme outperforms multi-paths approach using disjoint routes with regards to routing overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.11
• /
• pp.8-15
• /
• 2009

Side-channel attacks including the differential power analysis attack are often more powerful than classical cryptanalysis and have to be seriously considered by cryptographic algorithm's implementers. Various countermeasures have been proposed against such attacks. In this paper, we deal with the masking method, which is known to be a very effective countermeasure against the differential power analysis attack and propose new gate-level conversion methods between Boolean and arithmetic masks. The new methods require only 6n-5 XOR and 2n-2 AND gates with 3n-2 gate delay for converting n-bit masks. The basic idea of the proposed methods is that the carry and the sum bits in the ripple adder are manipulated in a way that the adversary cannot detect the relation between these bits and the original raw data. Since the proposed methods use only bitwise operations, they are especially useful for DPA-securely implementing cryptographic algorithms in hardware which use both Boolean and arithmetic operations. For example, we applied them to securely implement the block encryption algorithm SEED in hardware and present its detailed implementation result.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.48 no.6
• /
• pp.88-96
• /
• 2011

Underwater acoustic communication is applicable in various areas, such as ocean data collection, undersea exploration and development, tactical surveillance, etc. Thus, robot control system construction used for underwater-robot like AUV or ROV is essential in these areas. In this paper, we propose the Message Merging MAC($M^2$-MAC) protocol, which is suitable for real time robot control system, considering energy efficiency in important parts of underwater acoustic sensor network constitution. In this proposed MAC protocol, gateway node receives the data from robot nodes according to the time slots that were allotted previously. And messages delivered from base-station are generated to one MAC frame by buffering process. Finally, generated MAC frames are broadcasted to all robot nodes in the cluster. Our suggested MAC protocol can also be hybrid MAC protocol, which is successful blend of contention based and contention-free based protocol through relevant procedure with Maintenance&Sleep (M&S) period, when new nodes join and leave as an orphan. We propose mathematical analysis model concerned about End-to-End delay and energy consumption, which is important factor in constructing real-time robot control system. We also verify the excellence of performance according to comparison of existing MAC protocols with our scheme.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.5
• /
• pp.62-73
• /
• 2010

In this paper we proposed a candidate algorithm on G.711.1 and G.722 superwideband extension codec which is under standardization by ITU-T. The proposed codec not only provides an interoperable bitstream with ITU-T G.711.1 and G.722, but also encodes a superwideband signal with a bandwidth of 50-14,000 Hz using superwideband extension layer. The candidate codec consists of a core layer to provide an interoperability with conventional wideband codecs and superwideband extension layer using linear prediction-based sinusoidal coding. The proposed extension codec operates on 5ms frame and provides four superwideband bitrates of 64, 80, 96, and 112 kbit/s depending on the core codec. Since the resulting bitstream has an embedded structure, it can be converted into core bitstream by simple truncation without transcoding. The proposed codec has a short algorithmic delay and low complexity and passed the qualification test of G.711.1 and G.722 superwideband extension codec performed by ITU-T.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.4
• /
• pp.17-27
• /
• 2007

The enhanced distributed channel access (EDCA) of IEEE 802.11e has been standardized for supporting Quality of Service (QoS) in wireless LANs. In the EDCA, support of QoS can be achieved statistically by reducing the probability of medium access for lower priority traffics. In other words, it provides statistical channel access rather than deterministically prioritized access to high priority traffic. Therefore, lower priority traffics affect the performance of higher priority traffics. Consequently, at the high loads, the EDCA does not guarantee the QoS of multimedia applications such as voice and video even though it provides higher priority. In this paper, we propose a simple and effective scheme, called deterministic priority channel access (DPCA), for improving the QoS performance of the EDCA mechanism. In order to provide guaranteed priority channel access to multimedia applications, the proposed scheme uses a busy tone for limiting the transmissions of lower priority traffics when higher priority traffic has data packets to send. Performance of the proposed scheme is investigated by numerical analysis and simulation. Our results show that the proposed scheme outperforms the EDCA in terms of throughput, delay, jitter, and drop under a wide range of contention levels.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.2 s.332
• /
• pp.1-8
• /
• 2005

An area-efficient DC-DC voltage up-converter in a poly-Si TFT technology for system-on-glass is described which provides low-ripple output. The voltage up-converter is composed of charge-pumping circuit, comparator with threshold voltage mismatch compensation, oscillator, buffer, and delay circuit for multi-phase clock generation. The low ripple output is obtained by multi-phase clocking without increasing neither clock frequency nor filtering capacitor The measurement results have shown that the ripple on the output voltage with 4-phase clocking is 123mV, while Dickson and conventional cross-coupled charge pump has 590mV and 215mV voltage ripple, respectively, for $Rout=100k\Omega$, Cout-100pF, and fclk=1MHz. The filtering capacitor required for 50mV ripple voltage is 1029pF and 575pF for Dickson and conventional cross-coupled structure, for Iout=100uA, and fclk=1MHz, while the proposed multi-phase clocking DC-DC converter with 4-phase and 6-phase clocking requires only 290pF and 157pF, respectively. The efficiency of conventional and the multi-phase clocking DC-DC converter with 4-phase clocking is $65.7\%\;and\;65.3\%$, respectively, while Dickson charge pump has $59\%$ efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.8 s.338
• /
• pp.43-52
• /
• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.40 no.5
• /
• pp.397-409
• /
• 2003

This paper describes an implementation of radix-4 trellis parallel architecture and backward state transition control trace back Viterbi decoder, and presents the application results to high speed wireless LAN. The radix-4 parallelized architecture Vietrbi decoder can not only improve the throughput with simple structure, but also have small processing delay time and overhead circuit compared to M-step trellis architecture one. Based on these features, this paper addresses a novel Viterbi decoder which is composed of branch metric computation, architecture of ACS and trace back decoding by sequential control of backward state transition for the implementation of radix-4 trellis parallelized structure. With the proposed architecture, the decoding of variable code rate due to puncturing the base code can easily be implemented by the unified Viterbi decoder. Moreover, any additional circuit and/or peripheral control logic are not required in the proposed decoder architecture. The trace back decoding scheme with backward state transition control can carry out the sequential decoding according to ACS cycle clock without additional circuit for survivor memory control. In order to evaluate the usefulness, the proposed method is applied to channel CODEC of the IEEE 802.11a high speed wireless LAN, and HDL coding simulation results are presented.

• Journal of the Institute of Electronics Engineers of Korea SC
• /
• v.47 no.2
• /
• pp.25-34
• /
• 2010

This paper proposed a high-speed voltage-controlled ring-oscillator(VCRO) using a frequency doubling technique. The design of the proposed oscillator has been based on TSMC 0.18um 1.8V CMOS technology. The frequency doubling technique is achieved by AND-OR operations with 4 signals which have $90^{\circ}$ phase difference one another in one cycle. The proposed technique has been implemented using a 4-stage differential oscillator compose of differential latched inverters and NAND gates for AND and OR operations. The differential ring-oscillator can generate 4 output signals, which are $90^{\circ}$ out-of-phase one another, with low phase noise. The ANP-OR operations needed in the proposed technique are implemented using NAND gates, which is more area-efficient and provides faster switching speed than using NOR gates. Simulation results show that the proposed, VCRO operates in the frequency range of 3.72 GHz to 8 GHz with power consumption of 4.7mW at 4GHz and phase noise of ~-86.79dBc/Hz at 1MHz offset. Therefore, the proposed oscillator demonstrates superior performance compared with previous high-speed voltage-controlled ring-oscillators and can be used to build high-performance frequency synthesizers and phase-locked loops for radio-frequency applications.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.1 s.343
• /
• pp.111-120
• /
• 2006

In this paper, a node architecture of WDM metro network for connecting broadband access networks to converge wire/wireless networks. In consideration of the proposed node architecture and network requirements we proposed and evaluated medium access control protocols. We review WDM related technologies of sub-carrier multiplexing and optical components in order to resolve the bottleneck between optical backbone networks md access networks, and a access node architecture sharing common wavelength is introduced. Source-stripping (SS) MAC protocol Is evaluated under the proposed functional node architecture. DS+IS (Destination-Stripping and Source-Stripping) and DS+IS (Destination-Stripping and Intermediate-Stripping) MAC protocols are described to increase the slot-reuse factor which is low on SS MAC protocol. The key function of new MAC protocols regards the optical switch module of proposed node architecture and helps intermediate or source access nodes for dropping slots to destinations of different wavelength group. Thus, slot-reuse factor increases as the MAC protocols reduce the unnecessary ring-rotation of transferred slots. We use a numerical analysis to expect bandwidth efficiency and maximum throughput by slot-reuse factor Throughput network simulation, the verification of throughput, queuing delay, and transmission fairness are compared among MAC protocols.