• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.14 no.5
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• pp.209-214
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• 2014

IMS(IP Multi-Media Subsystem) is in the limelight as the Integrated wire and wireless Systems because of a sudden increase of smart mobile devices and growth of multimedia additional services such as IPTV. The structure of IMS is designed as a session control layer to provide various multimedia summative service using SIP based on IP communication network in order to carry out set-up, change and release by NGN of course, the existing voice services. But now It is broadly substituting in the IPTV, wire phone company and it is substituted in internet platform base on the soft-switch in currently. Especially, in currently, 4G LTE in a mobile communication company is rapidly growing in market. Therefore, in this study, we had designed and developed to the main prosser that can admit to 1000 user over and SIP gateway which can link the IMS Core that can link SIP Device which adopt the standard protocol on the SIP and to provide variable multimedia services.

• Journal of Advanced Navigation Technology
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• v.14 no.1
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• pp.57-65
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• 2010

In this paper, we propose the structure of heterogeneous multiprocessor's concept, which is the structure of the new type of the robot controller, and we introduce an integrating structure method, which is distributed multiprocessor within controller using sRIO. We also perform the computer simulation with using the sRIO IP core which was designed within FPGA as the method for implementation of integrated heterogeneous multiprocessor by sRIO communication. Thus, we verify the result.

• Smart Media Journal
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• v.3 no.4
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• pp.9-15
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• 2014

A virtual platform models a processor core and the peripheral devices constituting the SoC in software. Major companies utilize a variety of platforms for product development with optimal SW+SoC integrated system architecture design and IP reuse based Top-Down design flow using a virtual platform. In this paper, we propose a virtual platform based on OpenRISC, an open source RISC based core. The proposed virtual platform supports high speed emulation of approximately 20 MIPS using DBT (Dynamic Binary Translation).

• The Journal of the Korea Contents Association
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• v.2 no.2
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• pp.85-90
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• 2002

This paper presents tuo implementation models for wireless service operators to offer Mobile-IP over IMT-2000 Data service under IMT-2000 network by taking advantage of the existing infrastructure for IMT-2000 services. For this purpose, a new Mobile-IP over IMT-2000-based protocol architectures are introduced and service operation schemes and handoff schemes according to various scenarios of packet data services in the IMT-2000 core network are presented. Also, this paper describes the handoff scheme in terms of channel states.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.05a
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• pp.67-71
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• 2002

본 논문에서는 many-to-many IP 멀티캐스팅을 위한 효율적인 BCT(Backbone Core Tree)생성 알고리즘의 시뮬레이션 방법에 대하여 제안한다. BCT는 기법은 CBT(Core Based Tree)에 기반을 두고 있다. CBT는 공유 트리를 이용하여 멀티캐스트 자료를 전달하기 때문에 Source based Tree에 비하여 각 라우터가 유지해야 하는 상태 정보의 양에 적고, 적용하기 간단하지만, Core 라우터 선택의 어려움과 트래픽이 Core로 집중되는 문제점을 가지고 있다. 이에 대한 보완책으로 BCT기법이 제안되었는데, 본 논문에서는 주어진 네트워크 위상 그래프에서 최소신장 트리를 만들고, 센트로이드(Centroid)를 이용하여 효율적인 BCT를 생성하는 알고리즘을 제안하고 시뮬레이션 방법을 제시한다.

• Proceedings of the Korean Information Science Society Conference
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• 2000.10c
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• pp.117-119
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• 2000

UMTS(Universal Mobile Telecommunication System)의 Core Network에서는 SGSN(Serving GPRS Support Node)과 GGSN(Gateway GPRS Support Node)사이의 전송계층을 IP-Over-ATM network을 기반으로 한다. 이는 비연결형(connectionless) IP 트래픽들을 연결지향형(connectionoriented) ATM 전송계층을 통해 전송함으로 이때 효율적인 자원관리를 위해 적절한 VC(Virtual Circuit)의 접속과 해제를 수행해야 한다. 본 논문에서는 [1]에서 제안되는 GPRS(General Packer Radio Service)의 Web 트래픽 모델에 대하여 기존의 VC의 Holding-time을 결정하는 기법인 Holding Cost Pricing Model(LRU, Mean-Variance, Adaptive policy) [2]을 GGSN과 SGSN사이의 ATM 전송계층에 적용하였다. 각각의 기법들에서 VC의 이용률(utilization)과 설정율(setup rate)을 비교함으로써 Adaptive policy 기법의 성능이 다른 기법에 비해 효율적임을 알 수 있다.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.437-444
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• 2014

The integrated modular avionics (IMA) system has quite a number of line repalceable moduels (LRMs) in a cabinet. The LRM performs functions like line replaceable units (LRUs) in federated architecture. The video processing module (VPM) acts as a video bus bridge and gateway of ARINC 818 avionics digital video bus (ADVB). The VPM is a LRM in IMA core system. The ARINC 818 video interface and protocol standard was developed for high-bandwidth, low-latency and uncompressed digital video transmission. FPGAs of the VPM include video processing function such as ARINC 818 to DVI, DVI to ARINC 818 convertor, video decoder and overlay. In this paper we explain how to implement VPM's Hardware. Also we show the verification results about VPM functions and IP core performance.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2019.05a
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• pp.251-253
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• 2019

This paper describes an implementation of a security SoC (System-on-Chip) prototype that interfaces a microprocessor with a block cipher crypto-core. The Cortex-M0 was used as a microprocessor, and a crypto-core implemented by integrating ARIA and AES into a single hardware was used as an intellectual property (IP). The integrated ARIA-AES crypto-core supports five modes of operation including ECB, CBC, CFB, CTR and OFB, and two master key sizes of 128-bit and 256-bit. The integrated ARIA-AES crypto-core was interfaced to work with the AHB-light bus protocol of Cortex-M0, and the crypto-core IP was expected to operate at clock frequencies up to 50 MHz. The security SoC prototype was verified by BFM simulation, and then hardware-software co-verification was carried out with FPGA implementation.