• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.8B
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• pp.1469-1476
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• 2000

We have to consider the drain current as consisting of two components the vertical electric field and the longitudinal electric field because the drain current is almost totally due to the presence of drift in strong inversion of n-MOS FET. Especially the mobility of electrons in the inversion layer is smaller than the bulk mobility because the vertical electric field component that is generated by the effect of the gate voltage is perpendicular to the direction of normal current flow. By the multi-box segmentation technical method that are proposed in this paper we calculated the inversion layer depth and analyzed the vertical electric field component which has an large influence on mobility model.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.6
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• pp.11-21
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• 1997

The delay models for CMOS invertr presented so far predicted the delay time quite accurately whens input transition-time is very small. But the problem that the accuracy is inclined to decrease becomes apparent as input transition tiem increases. In this paper, a delay model for CMOS inverter is presented, which accuractely predicts the delay time even though input transition-time increases. To inverter must be included in modeling process because the main reason of inaccuracy as input transition tiem is the leakage current through the complementary MOS. For efficient modeling, this paper first models the MOSes with simple I-V charcteristic, with which both the pMOS and the nMOS are considered easily in calculating the inverter delay times. This resulting model needs few parameters and re-models each MOS effectively and simply evaluates output voltage to predict delay time, delay values obtained from this effectively and simply evaluates output voltage to predict delay time, delay values obtained from this model have been found to be within about 5% error rate of the SPICE results. The calculation time to predict the delay time with the model from this paper has the speed of more than 70times as fast as to the SPICE.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.241.1-241.1
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• 2013

최근 고집적화된 금속-산화막 반도체 metal oxide semiconductor (MOS) 소자는 크기가 점점 작아짐에 따라 얇은 산화막과 다양한 High-K 물질과 전극에 대하여 연구되고 있다. 이러한 소자의 열적 안정성과 균일성을 얻기 위해 다양한 열처리 방법이 사용되고 있으며, 일반적인 열처리 방법으로는 conventional thermal annealing (CTA)과 rapid thermal annealing (RTA)이 많이 이용되고 있다. 본 실험에서는 microwave radiation에 의한 열처리로 소자의 특성을 개선시킬 수 있다는 사실을 확인하였고, 상대적으로 $100^{\circ}C$ 이하의 저온에서도 공정이 이루어지기 때문에 열에 의한 소자 특성의 열화를 억제할 수 있으며, 또한 짧은 처리 시간 및 공정의 단순화로 비용을 효과적으로 절감할 수 있다. 본 실험에서는 metal-oxide-silicon (MOS) 구조의 capacitor를 제작한 다음, 기존의 CTA나 RTA 처리가 아닌 microwave radiation을 실시하여 MOS capacitor의 전기적인 특성에 미치는 microwave radiation 효과를 평가하였다. 본 실험은 p-type Si 기판에 wet oxidation으로 300 nm 성장된 SiO2 산화막 위에 titanium/aluminium (Ti/Al) 금속 전극을 E-beam evaporator로 형성하여 capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 평가하였다. 그 결과, microwave 처리를 통해 flat band voltage와 hysteresis 등이 개선되는 것을 확인하였고, microwave radiation 파워와 처리 시간을 최적화하였다. 또한 일반적인 CTA 열처리 소자와 비교하여 유사한 전기적 특성을 확인하였다. 이와 같은 microwave radiation 처리는 매우 낮은 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA나 RTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 산화막과 실리콘 기판의 계면 특성 개선에 매우 효과적이라는 것을 나타낸다. 따라서, microwave radiation 처리는 향후 저온공정을 요구하는 nano-scale MOSFET의 제작 및 저온 공정이 필수적인 display 소자 제작의 해결책으로 기대한다.

• The Journal of the Korea institute of electronic communication sciences
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• v.5 no.3
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• pp.275-280
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• 2010

In this paper, VoIP(Voice over Internet Protocol) transmission performance for MANET(Mobile Ad-hoc Networks) is improved and analyzed with packet aggregation scheme which is aggregating some of short length packets to one large packet and sending to networks. VoIP simulator based on NS(Network Simulator)-2 is implemented and used to measure performance of VoIP traffic transmission. In this simulation, VoIP traffics are generated with parameters of some codes such as G.711, G.729A, GSM.AMR and iBLC. MOS(Mean Opinion Score), end-to-end network delay, packet loss rate and transmission bandwidth are measured. Performance improvements of 98% for MOS, 6.4times for end-to-end network delay, 32times for packet loss rate is shown as simulation results. On the other hand, transmission bandwidth is increased about maximum 10%. Finally, VoIP implementation guide for the performance with packet aggregation is suggested.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.69-76
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• 2016

Current driving capability of MCT (MOS Controlled Thyristor) is determined by turn-off capability of conducting current, that is off-FET performance of MCT. On the other hand, having a good turn-on characteristics, including high peak anode current ($I_{peak}$) and rate of change of current (di/dt), is essential for pulsed power system which is one of major application field of MCTs. To satisfy above two requirements, careful control of on/off-FET performance is required. However, triple diffusion and several oxidation processes change surface doping profile and make it hard to control threshold voltage ($V_{th}$) of on/off-FET. In this paper, we have demonstrated the effect of $V_{th}$ adjustment ion implantation on the performance of MCT. The fabricated MCTs (active area = $0.465mm^2$) show forward voltage drop ($V_F$) of 1.25 V at $100A/cm^2$ and Ipeak of 290 A and di/dt of $5.8kA/{\mu}s$ at $V_A=800V$. While these characteristics are unaltered by $V_{th}$ adjustment ion implantation, the turn-off gate voltage is reduced from -3.5 V to -1.6 V for conducting current of $100A/cm^2$ when the $V_{th}$ adjustment ion implantation is carried out. This demonstrates that the current driving capability is enhanced without degradation of forward conduction and turn-on switching characteristics.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1999.05a
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• pp.411-414
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• 1999

70 ${\AA}$-thick oxides nitridied at various conditions were reoxidized at pemperatures of 900$^{\circ}C$ in dry-O$_2$ ambients for 5～40 mininutes. The gate oxide interface porperties as well as the oxide substrate interface properties of MOS(Metal Oxide Semiconductor) capacitors with various nitridation conditions, reoxidation conditions and pure oxidation condition were investigated. We stuided I$\sub$g/-V$\sub$g/ characteristics, $\Delta$V$\sub$g/ shift under constant current stress from electrical characteristics point of view and breakdown voltage from leakage current point of view of MOS capacitors with SiO$_2$, NO, RNO dielectrics. Overall, our experimental results show that reoxidized nitrided oxides show inproved charge trapping porperites, I$\sub$g/-V$\sub$g/ characteristics and gate $\Delta$V$\sub$g/ shift. It has also been shown that reoxidized nitridied oxide's leakage currented voltage is better than pure oxide's or nitrided oxide's from leakage current(1${\mu}$A) point of view.

• Journal of the Korea Computer Industry Society
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• v.6 no.5
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• pp.757-766
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• 2005

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6T Full CMOS SRAM had been continued as the technology advances, However, conventional 6T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6T Full CMOS SRAM is $70{\sim}90F^{2}$, which is too large compared to $8{\sim}9F^{2}$ of DRAM cell. With 80nm design rule using 193nm ArF lithography, the maximum density is 72M bits at the most. Therefore, pseudo SRAM or 1T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed $S^{3}$ cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^{3}$ SRAM cell technology with 100nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.4
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• pp.314-321
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• 2006

There have been great demands for higher density SRAM in all area of SRAM applications, such as mobile, network, cache, and embedded applications. Therefore, aggressive shrinkage of 6 T Full CMOS SRAM had been continued as the technology advances. However, conventional 6 T Full CMOS SRAM has a basic limitation in the cell size because it needs 6 transistors on a silicon substrate compared to 1 transistor in a DRAM cell. The typical cell area of 6 T Full CMOS SRAM is $70{\sim}90\;F^2$, which is too large compared to $8{\sim}9\;F^2$ of DRAM cell. With 80 nm design rule using 193 nm ArF lithography, the maximum density is 72 Mbits at the most. Therefore, pseudo SRAM or 1 T SRAM, whose memory cell is the same as DRAM cell, is being adopted for the solution of the high density SRAM applications more than 64 M bits. However, the refresh time limits not only the maximum operation temperature but also nearly all critical electrical characteristics of the products such as stand_by current and random access time. In order to overcome both the size penalty of the conventional 6 T Full CMOS SRAM cell and the poor characteristics of the TFT load cell, we have developed S3 cell. The Load pMOS and the Pass nMOS on ILD have nearly single crystal silicon channel according to the TEM and electron diffraction pattern analysis. In this study, we present $S^3$ SRAM cell technology with 100 nm design rule in further detail, including the process integration and the basic characteristics of stacked single crystal silicon TFT.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.06a
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• pp.8-9
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• 2006

Hafnium oxide ($HfO_2$) thin films were deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAHf and $O_3$. Prior to the deposition of $HfO_2$ films, a thin Hf ($10\;{\AA}$) metal layer was deposited. Deposition temperature of $HfO_2$ thin film was $350^{\circ}C$ and its thickness was $150\;{\AA}$. Samples were then annealed using furnace heating to temperature ranges from 500 to $900^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Thermally evaporated $3000\;{\AA}$-thick AI was used as top electrode. In this work, We study the interface characterization of $HfO_2$/Hf/Si MOS capacitor depending on annealing temperature. Through AES(Auger Electron Spectroscopy), capacitance-voltage (C-V) and current-voltage (I-V) analysis, the role of Hf layer for the better $HfO_2$/Si interface property was investigated. We found that Hf meta1 layer in our structure effective1y suppressed the generation of interfacial $SiO_2$ layer between $HfO_2$ film and silicon substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.2
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• pp.101-106
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• 2009

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition (ALD). We studied the electrical and material characteristics of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3$ at $350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. Round-type MOS capacitors have been fabricated on Si substrates with $2000\;{\AA}$-thick Pt top electrodes. The composition rate of the dielectric material was analyzed using TEM (Transmission Electron Microscopy), XRD (X-ray Diffraction) and XPS (X-ray Photoelectron Spectroscopy). Also the capacitance-voltage (C-V), conductance-voltage (G-V), and current-voltage (I-V) characteristics were measured. We calculated the density of oxide trap charges and interface trap charges in our MOS device. At the interface between $HfO_2$ and Si, both Hf-Si and Hf-Si-O bonds were observed, instead of Si-O bond. The sandwiched Hf metal layer suppressed the growing of $SiO_x$ layer so that $HfSi_xO_y$ layer was achieved. And finally, the generation of both oxide trap charge and interface trap charge in $HfO_2$ film was reduced effectively by using Hf metal layer.