• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.239-244
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• 2017

We experimentally investigate the physical mechanism for asymmetrical degradation in amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) under simultaneous gate and drain bias stresses. The transfer curves exhibit an asymmetrical negative shift after the application of gate-to-source ($V_{GS}$) and drain-to-source ($V_{DS}$) bias stresses of ($V_{GS}=24V$, $V_{DS}=15.9V$) and ($V_{GS}=22V$, $V_{DS}=20V$), but the asymmetrical degradation is more significant after the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20 V) nevertheless the vertical electric field at the source is higher under the bias stress ($V_{GS}$, $V_{DS}$) of (24 V, 15.9 V) than (22 V, 20 V). By using the modified external load resistance method, we extract the source contact resistance ($R_S$) and the voltage drop at $R_S$ ($V_{S,\;drop}$) in the fabricated a-IGZO TFT under both bias stresses. A significantly higher RS and $V_{S,\;drop}$ are extracted under the bias stress ($V_{GS}$, $V_{DS}$) of (22 V, 20V) than (24 V, 15.9 V), which implies that the high horizontal electric field across the source contact due to the large voltage drop at the reverse biased Schottky junction is the dominant physical mechanism causing the asymmetrical degradation of a-IGZO TFTs under simultaneous gate and drain bias stresses.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.833-836
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• 2005

Nano-gap trench is fabricated by the novel electrochemical etching technique using forward biased PN junction formed at the backside of the wafer. PN junction is formed using boron nitride wafer and the concentration of the boron doping is the high value of $1{\times}10^{19}$ $cm^{-3}$. The electro-chemical etching is performed in the 5% HF solution under the forward bias voltage of $1{\sim}2V$. The relationship between the etch rate of the trench and the voltage of the forward bias is investigated and the dependence of the gap for the voltage also examined. The etch rate increase from 0.027 ${\mu}m/min$ to 0.031 ${\mu}m/min$ as the value of the applied voltage increase from 1V to 2V, but the the gap is kept constant value of 40 nm.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.707-710
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• 2002

A 120kV/70A high voltage switch has been installed at Korea Atomic Energy Research Institute in Taejon to supply power with Korea Superconducting Tokamak Advanced Research (KSTAR) Neutral Beam Injection (NBI) system. NBI system requires fast cutoff of the power supply voltage for protection of the grid when arc detected and fast turn-on the voltage for sustaining the beam current. Therefore the high voltage switch and arc current detection circuit are important part of the NBI power supply and there are much need for high voltage solid state switches in NBI system and a broad area of applications. This switch consisted of 100 series connected MOSFETs and adopted the proposed simple and reliable gate drive circuit without bias supply, Various results taken during the commissioning phase with a 100kW resistive load and NBI source are shown. This paper presents the detailed design of 120kV/70A high voltage MOSFETs switch and simple gate drive circuit. Problems with the high voltage switch and gate driver and solutions are also presented.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.05a
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• pp.55-58
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• 1996

A new type CuN/Cu/CuN thin film electrode material with high adhesion to glass was developed by the dc reactive planar magnetron sputtering system for the PDP(Plasma Display Panel). The adhesive force of the CuxN thin film was in the range of 20∼40(N) under the conditions of the N$_2$ partial pressure of 15%, discharge current of 70mA, discharge voltage of 450v and substrate bias voltage of -100V. The adhesive force was depended on the N$_2$ partial Pressure, discharge current and substrate bias voltage.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.9
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• pp.527-532
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• 2000

The performance of ac plasma display panels (PDP) is influenced strongly by the surface glow discharge characteristics on the MgO thin films. This paper deals with the surface glow discharge characteristics and some physical properties of MgO thin films prepared by reactive RF planar unbalanced magnetron sputtering in connection with ac PDP. The samples prepared with dc bias voltage of -10V showed lower discharge voltage and lower erosion rate byion bombardment than those samples prepared by conventional magnetron sputtering or E-beam evaporation. The main factor that improves the discharge characteristics by bias voltage is considered to be due to the morphology changes or crystal structure of the MgO thin film by ion bombardement during deposition process.

• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.69.3-69.3
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• 2012

A high-performance low-voltage graphene field-effect transistor (FED array was fabricated on a flexible polymer substrate using solution-processable, high-capacitance ion gel gate dielectrics. The high capacitance of the ion gel, which originated from the formation of an electric double layer under the application of a gate voltage, yielded a high on-current and low voltage operation below 3 V. The graphene FETs fabricated on the plastic substrates showed a hole and electron mobility of 203 and 91 $cm^2/Vs$, respectively, at a drain bias of - I V. Moreover, ion gel gated graphene FETs on the plastic substrates exhibited remarkably good mechanical flexibility. This method represents a significant step in the application of graphene to flexible and stretchable electronics.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.186-192
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• 2012

Half-rail stacked drivers are used to reduce power consumption of the drivers for synchronous buck converters. In this paper, the stacked driver is optimized by matching the average charging and discharging currents used by high-side and low-side drivers. By matching the two currents, the average intermediate bias voltage can remain constant without the aid of the voltage regulator as long as the voltage ripple stays within the window defined by the hysteresis of the regulator. Thus the optimized driver in this paper can minimize the power consumption in the regulator. The current matching requirement yields the value for the intermediate bias voltage, which deviates from the half-rail voltage. Furthermore the required capacitance is also reduced in this design due to decreased charging current, which results in significantly reduced die area. The detailed analysis and design of the stacked driver is verified through simulations done using 5V MOSFET parameters of a typical 0.35-${\mu}m$ CMOS process. The difference in power loss between the conventional half-rail driver and the proposed driver is less than 1%. But the conventional half-rail driver has excess charge stored in the capacitor, which will be dissipated in the regulator unless reused by an external circuit. Due to the reduction in the required capacitance, the estimated saving in chip area is approximately 18.5% compared to the half-rail driver.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• Journal of the Korean Vacuum Society
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• v.8 no.4B
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• pp.541-547
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• 1999

Reactive ion etching process for InP using BCl3/O2/Ar high density inductively coupled plasma was investigated. The experimental design method proposed by the Taguchi was utilized to cover the whole parameter range while maintaining reasonable number of actual experiments. Results showed that the ICP power and the chamber pressure were the two dominant parameters affectsing etch results. It was also observed that the etch rate decreased and the surface roughness improved as the ICP power and the bias voltage increased and as the chamber pressure decreased. The Addition of oxygen to the gas mixture drastically improved surface roughness by suppressing the formation of the surface reaction product. The optimum condition was ICP power 600W, bias voltage -100V, 10% $O_2$, 6mTorr, and $180^{\circ}C$, resulting in about 0.15$\mu\textrm{m}$ etch rate with smooth surfaces and vertical mesa sidewalls Also, the maximum etch rate of abut 4.5 $\mu\textrm{m}$/min was obtained at the condition of ICP power 800W, bias voltage -150V, 15% $O_2$, 8mTorr and $160^{\circ}C$.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.238-241
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• 1999

Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.