• Proceedings of the KSRS Conference
• /
• 2007.10a
• /
• pp.522-525
• /
• 2007

Frame Synchronization is applied to not only digital data transmission for data synchronization between transmitter and receiver but also data communication with satellite. When satellite image data with high resolution and mass storage is transmitted, hardware frame synchronizer for real-time processing or software frame synchronizer for post-processing is used. In case of hardware, processing with high speed is available but data loss may happen for Search of Frame Synchronization. In case of software, data loss does not happen but speed is relatively slow. In this paper, Pending Buffer concept was proposed to cope with data loss according to processing status of Frame Synchronization. Algorithm to process Frame synchronization with high speed using bit threshold search algorithm with pattern search technique and SIMD is also proposed.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.36 no.8
• /
• pp.816-823
• /
• 2008

This paper describes the test results of developed high speed data processing unit using Xilinx GTP(Multi-Gigabit-Transceiver) interface and DDR-2 memory. The high speed data processing unit receives input data from packet generator at 1.25Gbps and transmits stored data to the data receiving system at 700Mbps. Therefore, DDR-2 memory controller and Xilinx GTP interface are implemented by FPGA instead of CPU to process high speed data directly.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.5
• /
• pp.74-86
• /
• 2002

This paper proposes a VLSI architecture for high-speed data processing of the differential phase detectors with the decision feedback. To improve the BER performance of the conventional differential phase detection, DF-DPD, DPD-RGPR and DFDPD-SA have been proposed. These detection methods have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, the VLSI architecture was proposed for high-speed data processing of the differential phase detectors with decision feedback. The Proposed architecture has the pre-calculation method to previously calculate the results on 'N'th step at 'M-1'th step and the pre-decision feedback method to previously feedback the predicted phases at 'M-1'th step. The architecture proposed in this paper was implemented to RTL using VHDL. The simulation results show that the Proposed architecture obtains the high-speed data processing.

• Proceedings of the Korea Institute of Convergence Signal Processing
• /
• 2003.06a
• /
• pp.110-113
• /
• 2003

In this paper, the multi-channel high speed data acquisition system is implemented. This high speed signal processing system for 3-D image display is applicable to the manipulation of a medical image processing, multimedia data and various fields of digital image processing. In order to convert the analog signal into digital one, A/D conversion circuit is designed. PCI interface method is designed and implemented, which is capable of transmission a large amount of data to computer. In order to, especially, channel extendibility of images acquisition, bus communication method is selected. By using this bus method, we can interface each module effectively. In this paper, 32-channel A/D conversion and PCI interface system for 3-dimensional and real-time display of the retina image is developed. The 32-channel image acquisition system and high speed data transmission system developed in this paper is applicable to not only medical image processing as 3-D representation of retina image but also various fields of industrial image processing in which the multi-point realtime image acquisition system is needed.

• Journal of the Korean Society for Aeronautical & Space Sciences
• /
• v.36 no.6
• /
• pp.616-620
• /
• 2008

High reliability is the important parameter on designing satellite system and it is also important to design hish speed data processing unit. To make high speed satellite processing unit, it is needed to utilize space processor, high speed data interface technology, mass memory control technology and data protection technology under space radiation environment.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.373-374
• /
• 2008

This paper proposes an architecture for high-speed data processing of the DF-DPD. The DF-DPD have the architecture feedbacking the detected phase to reduce the noise of the previous symbol as phase reference. However, the feedback of the detected phase results in lower data processing speed than that of the conventional differential phase detection. In this paper, an architecture is proposed for high-speed data processing of the differential phase detectors with decision feedback in the DF-DPD.

• Proceedings of the Korean Institute of Communication Sciences Conference
• /
• 1986.10a
• /
• pp.8-11
• /
• 1986

Data acquisition system is needed in signal analysis and processing by using computer. This paper realizes the high speed data acquisition system by using 8bit, 20MHZ refresh A/D converter and 18 x 64 Byte high speed memory. The high speed data acquisition system provides converted data to IBM-PC XT micro computer.

• Journal of Institute of Control, Robotics and Systems
• /
• v.10 no.2
• /
• pp.178-184
• /
• 2004

In this paper, we designed an image processing system for the high speed line-scan camera which adopts the new memory model we proposed. As a resolution and a data rate of the line-scan camera are becoming higher, the faster image processing systems are needed. But many conventional systems are not sufficient to process the image data from the line-scan camera during a very short time. We designed the memory controller which eliminates the time for transferring image data from the line-scan camera to the main memory with high-speed SRAM and has a dual-port configuration therefore the DSP can access the main memory even though the memory controller are writing the image data. The memory controller is implemented by VHDL and Xilinx SPARTAN-IIE FPGA.

• Proceedings of the KSRS Conference
• /
• 2007.10a
• /
• pp.526-529
• /
• 2007

Due to its inherent feature of high-resolution satellite, there is strong need in some specific area to minimize the processing time required to get a standard image on hand from downlink signal acquisition. However, in general image processing system, it takes considerable time to get image data up to certain level from raw data acquisition because the huge amount of data is dealt sequentially as input data. This paper introduces the high-speed image processing system which generates the image data only for the area selected by user. To achieve the high speed performance, this system includes Quick Look Image display function with sampling, ROI selection function, Image Line Index function, and Distributed processing function. The developed RPS was applied to KOMPSAT-2 320Mbps downlink channel and its effectiveness was successfully demonstrated. This feature to provide the image product very quickly is expected to promote the application of high resolution satellite image.

• The Transactions of the Korea Information Processing Society
• /
• v.1 no.1
• /
• pp.99-104
• /
• 1994

This paper proposes the method to process many pattern data 2-dimensionally at high speed in designing the physical of LSI. And this study shows that the switching network,which transmits pattern data between memory and processing elements at high speed on bidirection,has been designed using the barrel shifter and simulated with VHDL design system.