• Korean Journal of Materials Research
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• v.11 no.3
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• pp.236-242
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• 2001

HfN/Si$_3$N$_4$and NbN/Si$_3$N$_4$ multilayer coatings were deposited onto a high speed tool steel substrate by reactive sputtering and their mechanical properties were evaluated in terms of the dependence of hardness and adhesion strength on the sputter deposition process parameters. The hardnesses of both HfN/Si$_3$N$_4$and NbN/Si$_3$N$_4$ multiplayer coatings increase up to the flux ratio of 0.4 but nearly do not change after that as the $N_2$/Ar flux ratio in nitride sputter deposition increases. The hardnesses of both multiplayer coatings nearly do not change with annealing at low temperatures but decrease owing to oxidation with annealing at a high temperature like 80$0^{\circ}C$ after depositing the layers by sputtering. Post-annealing at low temperatures increases the adhesion strength of the multilayers. but high temperature annealing is not desirable since it decreases the adhesion strength besides the hardness deterioration.

• Journal of the Korean Magnetics Society
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• v.13 no.1
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• pp.6-14
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• 2003

The purpose of this study is to investigate the effect of chemical reaction with a bonding glass on physical and magnetic properties of Fe-Hf-N/SiO$_2$ and Fe-Hf-N/Cr/SiO$_2$ thin films. When the Fe-Hf-N/SiO$_2$ films were reacted with the bonding glass, the soft magnetic properties of them were extremely degraded. At $600^{\circ}C$, the saturation magnetization of the reacted film decreased to 1 kG, and its coercivity increased to 27 Oe, and its effective permeability decreased to 70. It was found that the degradation of soft magnetic properties of the Fe-Hf-N/SiO$_2$ films reacted with the bonding glass were attributed to the oxidation of the Fe-Hf-N layers to HfO$_2$ and Fe$_3$O$_4$. The soft magnetic properties of the Fe-Hf-N/Cr/SiO$_2$ films reacted with the bonding glass were degraded less than those of Fe-Hf-N/SiO$_2$ films. At $600^{\circ}C$, the saturation magnetization of the reacted film decreased to 13.5 kG, and its coercivity increased to 4 Oe, and its effective permeability decreased to 700. It was found that the Cr layer suppressed the oxidation of the Fe-Hf-N layers during the chemical reaction between the Fe-Hf-N layer and bonding glass.

• Journal of the Korean Ceramic Society
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• v.49 no.4
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• pp.333-336
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• 2012

The study to give electrical conductivity by dispersing carbon nanotubes (CNT) into silicon nitride ($Si_3N_4$) ceramics has been carried out in recent years. However, the density and the strength of $Si_3N_4$ ceramics were degraded and CNTs disappeared after firing at high temperatures because CNTs prevent $Si_3N_4$ from densification and there is a possibility that CNTs react with $Si_3N_4$ or $SiO_2$. In order to suppress the reaction and the disappearance of CNTs, lower temperature densification is needed. In this study, $HfO_2$ and $TiO_2$ was added to $Si_3N_4-Y_2O_3-Al_2O_3$-AlN system to fabricate CNT-dispersed $Si_3N_4$ ceramics at lower temperatures. $HfO_2$ promotes the densification of $Si_3N_4$ and prevents CNT from disappearance. As a result, the sample by adding $HfO_2$ and $TiO_2$ fired at lower temperatures showed higher electrical conductivity and higher bending strength. It was also shown that the mechanical and electrical properties depended on the quantity of the added CNTs.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.196-197
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• 2010

NAND형 charge trap flash (CTF) non-volatile memory (NVM) 소자가 30nm node 이하로 고집적화 되면서, 기존의 SONOS형 CTF NVM의 tunnel barrier로 쓰이는 SiO2는 direct tunneling과 stress induced leakage current (SILC)등의 효과로 인해 data retention의 감소 등 물리적인 한계에 이르렀다. 이에 따라 개선된 retention과 빠른 쓰기/지우기 속도를 만족시키기 위해서 tunnel barrier engineering (TBE)가 제안되었다. TBE NVM은 tunnel layer의 전위장벽을 엔지니어드함으로써 낮은 전압에서 전계의 민감도를 향상 시켜 동일한 두께의 단일 SiO2 터널베리어 보다 빠른 쓰기/지우기 속도를 확보할 수 있다. 또한 최근에 각광받는 high-k 물질을 TBE NVM에 적용시키는 연구가 활발히 진행 중이다. 본 연구에서는 Si3N4와 HfAlO (HfO2 : Al2O3 = 1:3)을 적층시켜 staggered의 새로운 구조의 tunnel barrier Capacitor를 제작하여 전기적 특성을 후속 열처리 온도와 방법에 따라 평가하였다. 실험은 n-type Si (100) wafer를 RCA 클리닝 실시한 후 Low pressure chemical vapor deposition (LPCVD)를 이용하여 Si3N4 3 nm 증착 후, Atomic layer deposition (ALD)를 이용하여 HfAlO를 3 nm 증착하였다. 게이트 전극은 e-beam evaporation을 이용하여 Al를 150 nm 증착하였다. 후속 열처리는 수소가 2% 함유된 질소 분위기에서 $300^{\circ}C$와 $450^{\circ}C$에서 Forming gas annealing (FGA) 실시하였고 질소 분위기에서 $600^{\circ}C{\sim}1000^{\circ}C$까지 Rapid thermal annealing (RTA)을 각각 실시하였다. 전기적 특성 분석은 후속 열처리 공정의 온도와 열처리 방법에 따라 Current-voltage와 Capacitance-voltage 특성을 조사하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.263-263
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• 2011

본 연구에서는 DBD (Dielectric Barrier Discharge)방식의 상압 플라즈마를 이용하여 FPD (flat panel display) 공정에 사용되는 a-Si, Si3N4의 식각 공정 특성을 평가하였다. 사용된 DBD 반응기는 기존의 blank planar plate 형태의 Power가 인가되는 anode 부분과 Dielectric Barrier 사이 공간을 액상의 도전체로 채워 넣은 형태의 전극이 사용 하였으며, 인가 Power는 40kHz AC 최대인가 전압 15 kVp를 사용 하였다. 방전 가스는 N2, 반응가스로는 CDA (Clean Dry Air)와 NF3, 액상의 Etchant를 사용 하였으며 모든 공정은 In-line type으로 시편을 처리 하였다. NF3의 경우 30 mm/sec 이송속도 1회 처리 기준 a-Si 1300${\AA}$, Si3N4 1900${\AA}$의 식각 두께를 보였으며 a-Si : Si3N4 선택비는 N2, CDA의 조절을 통하여 최대 1:2에서 4:1 정도까지 변화가 가능하였다. 균일도는 G2 (370 mm${\times}$470 mm)의 경우 5.8 %의 균일도를 보이고 있다. 이외에도 NF3 공정의 경우 실제 TFT-LCD 공정 중 n+ channel (n+ a-Si:H)식각 공정에 적용하여 5.5 inch LCD panel feasibility를 확인 할 수 있었다. 액상 Etchant (HF수용액, NH4HF2)는 버블러를 사용하여 기화 시켜 플라즈마 소스를 통해 1차적으로 활성화 시키고 기존 DBD 반응기에 공급해 주는 형태로 평가를 진행하였다. 식각 특성은 30mm/sec 이송속도에서 a-Si $25{\AA}$ 정도로 가스 형태의 Etchant에 비해 매우 낮은 수준이나 Etching rate 향상을 위한 factor 파악 및 개선을 위한 연구를 진행 하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.24-25
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• 2008

The effect of heat treatment in $HfO_2$ as charge trap with $SiO_2/Si_3N_4/SiO_2$ as tunnel oxide layer in capacitors has been investigated. Rapid thermal annealing (RTA) were carried out at the temperature range of 600 - $900^{\circ}C$. It is found that all devices carried out heat treatment have large threshold voltage shift Especially, device performed heat treatment at $900^{\circ}C$ has been confirmed the largest memory window. Also, Threshold voltage shift of device used conventional $SiO_2$ as tunnel oxide layer was smaller than that with $SiO_2/Si_3N_4/SiO_2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.34-34
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• 2009

The electrical characteristics of tunnel barrier engineered charge trap flash (TBE-CTF) memory with $SiO_2/Si_3N_4/SiO_2/Si$ engineered tunnel barrier, $HfO_2$ charge trap layer and $Al_2O_3$ blocking oxide layer (MAHONOS) were investigated. The energy bad diagram was designed by using the quantum-mechanical tunnel model (QM) and then the CTF memory devices were fabricated. As a result, the best thickness combination of MAHONOS is confirmed. Moreover, not enhanced P/E speed (Program: about $10^6$ times) (Erase: about $10^4$ times) but also enhanced retention and endurance characteristics are represented.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.2 s.31
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• pp.29-35
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• 2004

Hafnium-oxide gate dielectric films deposited by a metal organic chemical vapor deposition technique on a $N_2-plasma$ treated SiNx and a hydrogen-terminated Si substrate have been investigated. In the case of $HfO_2$ film deposited on a hydrogen-terminated Si substrate, suppressed crystallization with effective carbon impurity reduction was obtained at $450^{\circ}C$. X-ray photoelectron spectroscopy indicated that the interface layer was Hf-silicate rather than phase separated Hf-silicide and silicon oxide structure. Capacitance-voltage measurements show equivalent oxide thickness of about 2.6nm for a 5.0 nm $HfO_2/Si$ single layer capacitor and of about 2.7 nm for a 5.7 nm $HfO_2/SiNx/Si$ stack capacitor. TEM shows that the interface of the stack capacitor is stable up to $900^{\circ}C$ for 30 sec.

• Korean Journal of Optics and Photonics
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• v.3 no.4
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• pp.244-251
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• 1992

Buried Bragg filters of single mode $Si_{3}N_{4}$ rib waveguide with a cover layer of $SiO_{2}$ and grating at the interface of $Si_{3}N_{4}$ and $SiO_{2}$ are designed and fabricated. Etching of the grating on $Si_{3}N_{4}$ waveguide core by buffered HF showed uniform etching with good control up to 1 nm. This buried type of Bragg filters are immune to contamination of the surface of device. The mode index and bandwidth of filters are determined by measurements of the transmission spectrum of Bragg filters and compared with that of calculation. Waveguide Bragg filters loaded with the micro-heater of Cr film and the cladding of silicone rubber are made to control the Brag wavelength of the filter. As a result the filter wavelength of the device moved by 0.41 nm for 10 mA current to the shorter side of wavelength proportional to the square of the current.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2003.12a
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• pp.86-88
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• 2003

Gate 산화막을 high-k 물질인 $HfO_2$ 박막을 이용하여 N-type MOS field effect transistor를 제작하였다. 전극은 poly-Si 전극을 사용하였다. Gate 산화막은 ALD 로 $Hf(N(CH_3)_2)_4$ 원료를 이용하여 $HfO_2$ 박막을 형성하였다. 산화제는 $H_{2}O$ 와 $O_3$ 를 사용하였는데, $H_{2}O$ 가 약간 우수하였으나 그 차이는 크지 않았다. $HfO_2$ 를 증착하기 전에 in-situ 로 $O_3$ 를 흘려 줌으로써 $SiO_2$를 얇게 형성하였는데, 이 결과 threshold voltage 가 약 0.2V 높아지고 saturation current 가 커지는 것이 관찰되었다. 이러한 결과는 $HfO_2$ 박막을 직접 channel 위에 증착하는 것보다 $O_3$ 를 이용 얇은 $SiO_2$ 를 형성하고 그 위에 $HfO_2$ 박막을 증착하는 방법이 transistor의 특성을 향상시키는 데 도움이 된다.