• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.6
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• pp.445-449
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• 2020

Non-volatile memory is approaching its fundamental limits with the Si₃N₄ storage layer, necessitating the use of alternative materials to achieve a higher programming/erasing speed, larger storage window, and better data retention at lower operating voltage. This limitation has restricted the development of the charge-trap memory, but can be addressed by using high-k dielectrics. The paper reviews the doping of nitrogen, titanium, and yttrium on high-k dielectrics as a storage layer by comparing MONOS devices with different storage layers. The results show that nitrogen doping increases the storage window of the Gd₂O₃ storage layer and improves its charge retention. Titanium doping can increase the charge capture rate of HfO₂ storage layer. Yttrium doping increases the storage window of the BaTiO₃ storage layer and improves its fatigue characteristics. Parameters such as the dielectric constant, leakage current, and speed of the memory device can be controlled by maintaining a suitable amount of external impurities in the device.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.6
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• pp.1175-1180
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• 2022

STI has been studied a lot as a process technology for wide area planarization according to miniaturization and high integration of semiconductor devices. In this study, as methods for improving the STI profile, wet etching of pad oxide using hydrofluorine solution and dry etching of O₂+CF₄ after STI dry etching were proposed. This process technology showed improvement in profile imbalance and leakage current between patterns according to device density compared to the conventional method. In addition, as a result of measuring the HLD thickness after CMP for a device having the same STI depth and HLD deposition, the measured value was different depending on the device density. It was confirmed that this was due to the difference in the thickness of the nitride film according to the device density after CMP and the selectivity of the slurry.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Proceedings of the KIEE Conference
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• 1999.07d
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• pp.1919-1921
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• 1999

AlN thin films were fabricated by sputter for the application of MIS device with Al/AlN/Si structure. We controled that sub-temperature room-temperature. Sputtering pressure 5 mTorr, flow ratio Ar:$N_2$=1:1(4sccm:4sccm), and appended hydrogen gas $0{\sim}5%$. AlN thin films thickness fabricated to maintain $2700{\AA}$ time control. Before the experiment remove to the contaminated material use the Ultrasonic every 10 minute use the acetone and ethanol, then use the HF remove oxide-substance at 10 second. To analyze characteristic of the $H_2$ gas addition period, C-V and I-V characteristic make and experiment $H_2$ gas at addition period progressive capability of I-V and C-V characteristic.

• Journal of the Korean institute of surface engineering
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• v.41 no.5
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• pp.189-193
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• 2008

In this study, we carried out an investigation of the etching characteristics (etch rate, selectivity to $SiO_2$ and $HfO_2$) of TiN thin films in the $CH_4$/Ar inductively coupled plasma. The maximum etch rate of $274\;{\AA}/min$ for TiN thin films was obtained at $CH_4$(80%)/Ar(20%) gas mixing ratio. At the same time, the etch rate was measured as function of the etching parameters such as RF power, Bias power, and process pressure. The X-ray photoelectron spectroscopy analysis showed an efficient destruction of the oxide bonds by the ion bombardment as well as showed an accumulation of low volatile reaction products on the etched surface. Based on these data, the ion-assisted chemical reaction was proposed as the main etch mechanism for the $CH_4$ containing plasmas.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.165-165
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• 2012

비정질의 Tantalum-indium-zinc oxide (TIZO) 박막 트랜지스터는 RF-sputtering 방법으로 증착되었으며 소결된 단일 타겟을 사용하였다. 증착당시 반응 가스는 알곤과 산소를 95 : 5로 섞어 반응성 스퍼터링을 진행하였으며, 1 mtorr에서 5 mtorr까지 다양한 공정압력에서 증착한 이 후 Furnace system을 통하여 $350^{\circ}C$의 온도로 1시간 동안 후열처리 공정을 진행하였다. 비정질 TIZO 박막을 활성 층으로 사용하여 제작한 박막 트랜지스터는 공정압력이 낮아짐에 따라 높은 이동도와 낮은 subthrehsold gate swing 보였다. 이러한 현상의 원인을 규명하고자 물리적, 전기적, 광학적 분석을 통하여 공정압력의 변화가 박막 트랜지스터 구동에 미치는 영향을 해석하였다. 우선 공정압력에 따른 TIZO 박막의 Ta, In, Zn, O 각각의 조성을 분석하기 위하여 Rutherford back scattering (RBS) 분석을 실시하였다. 또한 X-선 회절(X-ray diffraction)분석을 통해 열처리된 TIZO 박막은 공정압력에 따라 물리적 구조의 변화를 일으키지 않으며 모든 박막은 비정질상을 보이는 것을 확인하였다. 3.3eV의 광학적 밴드 갭은 기존에 보고되었던 비정질 산화물 반도체(InGaZnO, HfInZnO 등)와도 유사한 밴드갭을 가지고 있음을 확인하였다. 또한, spectroscopic ellipsometry (SE)분석을 통하여 전도대 이하 밴드 갭 내에 존재하는 결함상태 및 전도대에서 결함상태까지의 에너지 준위 그리고 공정압력에 따라 결함의 양과 발생되는 에너지 준위가 변화하는 현상을 관측하였다. 박막을 제조 할 때의 공정압력은 박막 내의 결함의 양 및 발생되는 에너지 준위의 변화를 야기하고 변화된 결함의 양과 발생된 에너지 준위에 따라 박막트랜지스터의 전기적 특성을 변화시킨다는 결과를 도출하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.78-79
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• 2009

본 연구에서는 ZnO계 투명전극 소재를 이용하여 RFID 태그 안테나에 적용 가능성 여부를 확인하였다. Si 기판위에 RF 스퍼터링 공정에 의해 Ga-doped ZnO 투명 마이크로스트립 스파이혈 안테나를 $2{\mu}m$를 증착하여 구현하고 그 전기적 특성을 측정하였다. HFSS 전자계 시뮬레이터를 사용하여 13.56MHz HF 주파수 대역에서 태그 안테나로서의 가능성을 검증한 후 Ga-doped ZnO 타겟을 사용한 RF 스퍼터링 공정에 의하여 스파이럴 안테나 패턴을 구현하였다. 마이크로스트립 선폭 및 선 간격을 $50\sim200{\mu}m$때 영역에서 조절하면서 안테나 패턴을 설계하였다. S 파라메터, 자기공진주파수 및 Q값을 시뮬레이션으로부터 도출하였다. Al $2{\mu}m$ 증착한 시편에 비하여 약 -10dB 정도의 이득저하가 발생하였으나 리더-태그를 밀착시킨 조건에서 1.7V (13.56MHz) 전압검출이 가능하였다.

• 한국신재생에너지학회:학술대회논문집
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• 2011.05a
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• pp.130.2-130.2
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• 2011

본 연구에서는 RF magnetron sputtering을 이용하여 실리콘 박막 태양전지용 ZnO:Al 전면전극을 제작하고 다양한 식각조건에 따른 ZnO:Al 박막의 표면형상 변화와 함께 전기적 및 광학적 특성 변화를 조사하였다. pin 구조를 갖는 실리콘 박막 태양전지의 효율 향상을 위해서는 입사광의 산란효과에 따른 광포획 증가가 필수적이며 이를 위하여 ZnO:Al 전면전극의 표면텍스처링 형성이 필요하다. 식각용액으로는 HCl과 HF 등을 사용하였으며 식각용액 농도 및 식각시간을 변화시켰다. 식각 후의 ZnO:Al 박막의 표면형상은 SEM(Scanning Electron Microscope)과 AFM(Atomic Force Microscope)을 이용하여 분석을 하였고, UV-visible-nIR spectrometer를 이용하여 총 투과도 및 산란 투과도를 측정하였다. 이 외에도 four-point probe 및 Hall measurement를 이용하여 전기적 특성 변화를 조사하였다. 다양한 식각조건에 따라 제조된 ZnO:Al 박막 위에 실리콘 박막 태양전지를 제작하여 전면전극의 표면형상에 따른 태양전지 성능변화를 비교 분석하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.10
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• pp.615-624
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• 2017

This study investigated the various physical and electrical effects of silicon direct bonding. Direct bonding means the joining of two wafers together without an intermediate layer. If the surfaces are flat, and made clean and smooth using HF treatment to remove the native oxide layer, they can stick together when brought into contact and form a weak bond depending on the physical forces at room temperature. An IR camera and acoustic systems were used to analyze the voids and bonding conditions in an interface layer during bonding experiments. The I-V and C-V characteristics are also reported herein. The capacitance values for a range of frequencies were measured using a LCR meter. Direct wafer bonding of silicon is a simple method to fuse two wafers together; however, it is difficult to achieve perfect bonding of the two wafers. The direct bonding technology can be used for MEMS and other applications in three-dimensional integrated circuits and special devices.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.166-173
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• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.